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1. 发明申请

US20050253622A1 Circuit for generating a tracking reference voltage 失效
标题翻译：用于产生跟踪参考电压的电路
公开(公告)号：US20050253622A1
公开(公告)日：2005-11-17
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao Truong
IPC分类号： H03K17/16 , H04L25/06 , H04L25/45
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译：两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

2. 发明授权

US07239213B2 Reduced cross-talk signaling circuit and method 失效
公开(公告)号：US07239213B2
公开(公告)日：2007-07-03
申请号：US11209549
申请日：2005-08-23
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H01P1/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

3. 发明授权

US08018837B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

4. 发明授权

US07208972B2 Circuit for generating a tracking reference voltage 失效
标题翻译：用于产生跟踪参考电压的电路
公开(公告)号：US07208972B2
公开(公告)日：2007-04-24
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
IPC分类号： H03K17/16
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译：两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

5. 发明授权

US06930507B2 Thevenins receiver 失效
标题翻译：戴维宁接收器
公开(公告)号：US06930507B2
公开(公告)日：2005-08-16
申请号：US10616845
申请日：2003-07-10
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.
摘要翻译：终端网络具有多个电阻器，其形成具有公共节点的多个分压器。一半的电阻器与P沟道场效应晶体管（PFET）耦合到正电源电压，另一半电阻与N沟道FET（NFET）耦合到负极或接地电源电压。逻辑信号用于控制FET的栅极。通过修改哪些FET为ON，可以选择性地控制终端网络以产生具有相同阻抗水平的各种偏移电平。阻抗水平也可以被修改，同时保持相同的偏移水平。可以选择性地采用延迟电路来在所选择的延迟时间之后反馈控制信号以调整阈值电平以动态地或静态地优化信号接收。

6. 发明授权

US08050174B2 Self-healing chip-to-chip interface 失效
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

7. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

8. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

9. 发明授权

US08089813B2 Controllable voltage reference driver for a memory system 失效
标题翻译：用于存储系统的可控参考电压驱动器
公开(公告)号：US08089813B2
公开(公告)日：2012-01-03
申请号：US12175555
申请日：2008-07-18
申请人： Daniel M. Dreps
发明人： Daniel M. Dreps
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C5/04 , G11C5/063 , G11C5/147 , G11C8/08 , G11C29/021 , G11C29/028
摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.
摘要翻译：电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准输出节点。可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

10. 发明申请

US20110289270A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA TRANSFER MANAGEMENT 有权
标题翻译：用于数据传输管理的系统，方法和计算机程序产品
公开(公告)号：US20110289270A1
公开(公告)日：2011-11-24
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
摘要翻译：根据本公开的一个方面，公开了一种用于管理数据传送的方法和技术。该方法包括将由数据处理系统的处理器单元将要写入存储器子系统的数据与存储的数据模式进行比较，并且响应于确定数据与存储的数据模式匹配，用模式标签替换匹配数据对应于匹配的数据模式。该方法还包括将模式标签发送到存储器子系统。

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