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1. 发明申请

US20140240326A1 Method, Apparatus, System For Representing, Specifying And Using Deadlines 有权
标题翻译：方法，设备，代表，指定和使用期限的系统
公开(公告)号：US20140240326A1
公开(公告)日：2014-08-28
申请号：US13780117
申请日：2013-02-28
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

2. 发明申请

US20140201471A1 Arbitrating Memory Accesses Via A Shared Memory Fabric 有权
标题翻译：仲裁存储器通过共享存储器访问
公开(公告)号：US20140201471A1
公开(公告)日：2014-07-17
申请号：US13743795
申请日：2013-01-17
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
IPC分类号： G06F13/16
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

3. 发明申请

US20140201500A1 Controlling Bandwidth Allocations In A System On A Chip (SoC) 有权
标题翻译：控制片上系统中的带宽分配（SoC）
公开(公告)号：US20140201500A1
公开(公告)日：2014-07-17
申请号：US13743833
申请日：2013-01-17
申请人： Jose S. Niell , Ramadass Nagarajan
发明人： Jose S. Niell , Ramadass Nagarajan
IPC分类号： G06F15/78
CPC分类号： G06F15/7807 , G06F13/4059 , G06F21/70 , G06F2213/0026 , G06F2213/0038 , G06F2221/2101 , G06F2221/2141 , H04L47/622
摘要： In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，诸如芯片上的系统的处理器的结构包括至少一个数据缓冲器，其包括多个条目，每个条目用于存储要传送到多个代理和从存储器传送到和从存储器传输的数据，请求跟踪器，以跟踪要输出到结构的有序域的待处理请求;以及输出节流逻辑，用于控制从核心代理的写入事务和从存储器读取完成事务之间对有序域的分配。描述和要求保护其他实施例。

4. 发明申请

US20090013160A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 有权
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：US20090013160A1
公开(公告)日：2009-01-08
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

5. 发明授权

US08180997B2 Dynamically composing processor cores to form logical processors 有权
标题翻译：动态组成处理器内核以形成逻辑处理器
公开(公告)号：US08180997B2
公开(公告)日：2012-05-15
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F15/76
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

6. 发明授权

US09405688B2 Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture 有权
标题翻译：用于处理分布式存储器结构架构中的地址冲突的方法，装置，系统
公开(公告)号：US09405688B2
公开(公告)日：2016-08-02
申请号：US13785908
申请日：2013-03-05
申请人： Ramadass Nagarajan , Robert G. Milstrey , Michael T. Klinglesmith
发明人： Ramadass Nagarajan , Robert G. Milstrey , Michael T. Klinglesmith
IPC分类号： G06F12/08 , G06F12/0815 , G06F12/0806 , G06F12/0844 , G06F12/02
CPC分类号： G06F12/0815 , G06F12/02 , G06F12/08 , G06F12/0806 , G06F12/0844 , G06F2212/621
摘要： Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.
摘要翻译：用于处理分布式存储器结构中的地址冲突的方法，装置和系统。来自计算机系统中的高速缓存代理和输入/输出（I / O）代理的存储器访问请求通过使用并行管道的分布式存储器结构架构并行地进行服务，同时保持与高速缓存代理相关联的高速缓存存储器的内存一致性并执行存储器访问订购源自I / O代理的内存访问请求。

7. 发明申请

US20140258620A1 METHOD, APPARATUS, SYSTEM FOR HANDLING ADDRESS CONFLICTS IN A DISTRIBUTED MEMORY FABRIC ARCHITECTURE 有权
标题翻译：方法，装置，处理分布式存储器织物结构中的地址冲突的系统
公开(公告)号：US20140258620A1
公开(公告)日：2014-09-11
申请号：US13785908
申请日：2013-03-05
申请人： Ramadass Nagarajan , Robert G. Milstrey , Michael T. Klinglesmith
发明人： Ramadass Nagarajan , Robert G. Milstrey , Michael T. Klinglesmith
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/02 , G06F12/08 , G06F12/0806 , G06F12/0844 , G06F2212/621
摘要： Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.
摘要翻译：用于处理分布式存储器结构中的地址冲突的方法，装置和系统。来自计算机系统中的高速缓存代理和输入/输出（I / O）代理的存储器访问请求通过使用并行管道的分布式存储器结构架构并行地进行服务，同时保持与高速缓存代理相关联的高速缓存存储器的内存一致性并执行存储器访问订购源自I / O代理的内存访问请求。

8. 发明申请

US20050005084A1 Scalable processing architecture 审中-公开
标题翻译：可扩展处理架构
公开(公告)号：US20050005084A1
公开(公告)日：2005-01-06
申请号：US10829668
申请日：2004-04-22
申请人： Douglas Burger , Stephen Keckler , Karthikeyan Sankaralingam , Ramadass Nagarajan
发明人： Douglas Burger , Stephen Keckler , Karthikeyan Sankaralingam , Ramadass Nagarajan
IPC分类号： G06F9/44 , G06F15/00 , G06F15/80
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

9. 发明申请

US20150082002A1 DYNAMIC HETEROGENEOUS HASHING FUNCTIONS IN RANGES OF SYSTEM MEMORY ADDRESSING SPACE 有权
标题翻译：系统记忆空间范围内的动态异质冲击函数
公开(公告)号：US20150082002A1
公开(公告)日：2015-03-19
申请号：US14031398
申请日：2013-09-19
申请人： Jorge E. Parra , Joydeep Ray , Ramadass Nagarajan
发明人： Jorge E. Parra , Joydeep Ray , Ramadass Nagarajan
IPC分类号： G06F12/10
CPC分类号： H04L9/3242 , G06F12/0607 , G06F13/16
摘要： Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.
摘要翻译：描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。

10. 发明申请

US20080244230A1 SCALABLE PROCESSING ARCHITECTURE 有权
标题翻译：可扩展的处理结构
公开(公告)号：US20080244230A1
公开(公告)日：2008-10-02
申请号：US12136645
申请日：2008-06-10
申请人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
发明人： Douglas C. Burger , Stephen W. Keckler , Karthikevan Sankaralingam , Ramadass Nagarajan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F15/8007 , G06F9/4494
摘要： A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes. An article according to an embodiment of the invention includes a medium having instructions which are capable of causing a machine to partition a program into a plurality of groups of instructions, assign one or more of the instruction groups to a plurality of interconnected preselected computation nodes, load the instruction groups on to the nodes, and execute the instruction groups as each instruction in each group receives all necessary associated operands for execution.
摘要翻译：根据本发明的各种实施例的计算节点包括能够耦合到至少一个第一其他计算节点的至少一个输入端口，耦合到所述输入端口以存储输入数据的第一存储器，用于接收的第二存储器并且存储指令，将输入数据与指令相匹配的指令唤醒单元，使用输入数据产生输出数据的执行指令的至少一个执行单元，以及至少能够耦合到至少一个第二个其他计算节点。节点还可以包括将输出数据从输出端口引导到第二另一个节点的路由器。根据本发明的各种实施例的系统包括用于获取一组指令的外部指令定序器和一个或多个互连的预先选择的计算节点。根据本发明的实施例的物品包括具有能够使机器将程序分成多组指令的指令的介质，将一个或多个指令组分配给多个互连的预选计算节点，将指令组加载到节点，并执行指令组，因为每个组中的每个指令都接收所有必需的相关操作数以供执行。

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