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1. 发明申请

US20050121768A1 Silicon chip carrier with conductive through-vias and method for fabricating same 有权
标题翻译：具有导电通孔的硅芯片载体及其制造方法
公开(公告)号：US20050121768A1
公开(公告)日：2005-06-09
申请号：US10729254
申请日：2003-12-05
申请人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
发明人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
IPC分类号： H01L21/48 , H01L21/768 , H01L23/498 , H01L23/48 , H01L21/4763
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译：一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于或者与衬底的密切匹配。导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯，具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

2. 发明申请

US20060027934A1 Silicon chip carrier with conductive through-vias and method for fabricating same 审中-公开
标题翻译：具有导电通孔的硅芯片载体及其制造方法
公开(公告)号：US20060027934A1
公开(公告)日：2006-02-09
申请号：US11242221
申请日：2005-10-03
申请人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
发明人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
IPC分类号： H01L23/48
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译：一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于或者与衬底的密切匹配。导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯，具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

3. 发明申请

US20050037608A1 Deep filled vias 有权
标题翻译：深填充的通孔
公开(公告)号：US20050037608A1
公开(公告)日：2005-02-17
申请号：US10639989
申请日：2003-08-13
申请人： Panayotis Andricacos , Emanuel Cooper , Timothy Dalton , Hariklia Deligianni , Daniel Guidotti , Keith Kwietniak , Michelle Steen , Cornelia Tsang
发明人： Panayotis Andricacos , Emanuel Cooper , Timothy Dalton , Hariklia Deligianni , Daniel Guidotti , Keith Kwietniak , Michelle Steen , Cornelia Tsang
IPC分类号： H01L21/288 , H01L21/3065 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/30655 , H01L21/76898
摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.
摘要翻译：提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接的通道。尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。

4. 发明申请

US20080083697A1 POROUS SILICON COMPOSITE STRUCTURE AS LARGE FILTRATION ARRAY 审中-公开
标题翻译：多孔硅复合结构作为大的过滤阵列
公开(公告)号：US20080083697A1
公开(公告)日：2008-04-10
申请号：US11872693
申请日：2007-10-15
申请人： Timothy Dalton , Michelle Steen
发明人： Timothy Dalton , Michelle Steen
IPC分类号： C23F1/00
CPC分类号： B01D67/0062 , B01D67/0034 , B01D67/0072 , B01D67/0079 , B01D69/10 , B01D69/12 , B01D71/02 , B01D71/64 , B01D71/68 , B01D2325/022 , B01D2325/08 , B01D2325/24
摘要： A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.
摘要翻译：在几个示例性版本中公开了一种新型的不对称滤膜和制造方法。膜结构物理坚固，适用于各种应用。支撑膜可以由诸如多孔硅或氧化硅的材料构成，并且分离膜可以由诸如聚合物，沸石膜或氧化硅的材料构成。该过程依赖于微电子行业的改进。

5. 发明申请

US20080026551A1 FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS 失效
标题翻译：使用双自对准硅胶工艺形成全硅酸金属门
公开(公告)号：US20080026551A1
公开(公告)日：2008-01-31
申请号：US11830277
申请日：2007-07-30
申请人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
发明人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译：提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

6. 发明申请

US20050092676A1 Porous silicon composite structure as large filtration array 有权
标题翻译：多孔硅复合结构作为大过滤阵列
公开(公告)号：US20050092676A1
公开(公告)日：2005-05-05
申请号：US10697077
申请日：2003-10-30
申请人： Timothy Dalton , Michelle Steen
发明人： Timothy Dalton , Michelle Steen
IPC分类号： B01D67/00 , B01D69/10 , B01D69/12 , B01D71/02 , B01D71/04
CPC分类号： B01D67/0062 , B01D67/0034 , B01D67/0072 , B01D67/0079 , B01D69/10 , B01D69/12 , B01D71/02 , B01D71/64 , B01D71/68 , B01D2325/022 , B01D2325/08 , B01D2325/24
摘要： A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.
摘要翻译：在几个示例性版本中公开了一种新型的不对称滤膜和制造方法。膜结构物理坚固，适用于各种应用。支撑膜可以由诸如多孔硅或氧化硅的材料构成，并且分离膜可以由诸如聚合物，沸石膜或氧化硅的材料构成。该过程依赖于微电子行业的改进。

7. 发明申请

US20070281431A1 FORMATION OF FULLY SILICIDED (FUSI) GATE USING A DUAL SILICIDE PROCESS 有权
标题翻译：使用双硅酸过程形成全硅（FUSI）门
公开(公告)号：US20070281431A1
公开(公告)日：2007-12-06
申请号：US11840774
申请日：2007-08-17
申请人： Glenn Biery , Ghavam Shahidi , Michelle Steen
发明人： Glenn Biery , Ghavam Shahidi , Michelle Steen
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/28097 , H01L21/28518 , H01L29/51 , H01L29/66545
摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.
摘要翻译：一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构源极/漏极区域在栅极盐化过程中。所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

8. 发明申请

US20070138563A1 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US20070138563A1
公开(公告)日：2007-06-21
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
发明人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

9. 发明申请

US20070032010A1 Formation of fully silicided (FUSI) gate using a dual silicide process 失效
公开(公告)号：US20070032010A1
公开(公告)日：2007-02-08
申请号：US11195994
申请日：2005-08-02
申请人： Glenn Biery , Ghavam Shahidi , Michelle Steen
发明人： Glenn Biery , Ghavam Shahidi , Michelle Steen
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/6656 , H01L21/28097 , H01L21/28518 , H01L29/51 , H01L29/66545
摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

10. 发明申请

US20050112896A1 Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory 失效
标题翻译：包括相同的多位相变存储单元和多位相变存储器，形成多位相变存储器的方法，以及编程多位相变存储器的方法
公开(公告)号：US20050112896A1
公开(公告)日：2005-05-26
申请号：US10718070
申请日：2003-11-20
申请人： Hendrik Hamann , Chung Lam , Michelle Steen , Hon-Sum Wong
发明人： Hendrik Hamann , Chung Lam , Michelle Steen , Hon-Sum Wong
IPC分类号： G11C11/56 , G11C16/02 , H01L21/311 , H01L27/24 , H01L45/00
CPC分类号： H01L45/06 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A multi-bit phase change memory cell including a stack of a plurality of conductive layers and a plurality of phase change material layers, each of the phase change material layers disposed between a corresponding pair of conductive layers and having electrical resistances that are different from one another.
摘要翻译：一种多位相变存储单元，包括多个导电层和多个相变材料层的堆叠，每个相变材料层设置在相应的一对导电层之间并且具有不同于一个导电层的电阻另一个。

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