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1. 发明授权

US5212662A Floating point arithmetic two cycle data flow 失效
标题翻译：浮点数算术两个循环数据流
公开(公告)号：US5212662A
公开(公告)日：1993-05-18
申请号：US580892
申请日：1990-09-11
申请人： Daniel Cocanougher , Robert K. Montoye , Myhong Nguyenphu , Stephen L. Runyon
发明人： Daniel Cocanougher , Robert K. Montoye , Myhong Nguyenphu , Stephen L. Runyon
IPC分类号： G06F7/544 , G06F7/57
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49947
摘要： A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
摘要翻译：提供一种用于执行浮点算术运算的处理器，其包括对第一周期中的一组操作数执行第一浮点算术运算的电路和对操作数的第二浮点运算和第一浮点运算结果在第二周期的算术运算。提供一种控制电路，用于在第三个周期内将第二浮动操作的结果传送到第一浮点运算，用于在下一个连续循环中进行第一浮点运算，同时舍入第二浮点运算的结果。

2. 发明授权

US4999802A Floating point arithmetic two cycle data flow 失效
标题翻译：浮点算术两周期数据流
公开(公告)号：US4999802A
公开(公告)日：1991-03-12
申请号：US297781
申请日：1989-01-13
申请人： Daniel Cocanougher , Robert K. Montoye , Myhong Nguyenphu , Stephen L. Runyon
发明人： Daniel Cocanougher , Robert K. Montoye , Myhong Nguyenphu , Stephen L. Runyon
IPC分类号： G06F7/38 , G06F7/485 , G06F7/487 , G06F7/527 , G06F7/544 , G06F7/57
CPC分类号： G06F9/3889 , G06F7/483 , G06F7/5443 , G06F7/49947
摘要： A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

3. 发明授权

US08902690B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

4. 发明授权

US08687398B2 Sense scheme for phase change material content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的感应方案
公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译：一种用于感测内容可寻址存储器中匹配线的感测电路和方法。感测电路包括电反馈回路中电耦合到匹配线的反相器。逆变器包括匹配线的反相阈值。在预充电阶段期间，将匹配线充电至基本上第一电压阈值。当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

5. 发明授权

US08295056B2 Silicon carrier structure and method of forming same 有权
标题翻译：硅载体结构及其形成方法
公开(公告)号：US08295056B2
公开(公告)日：2012-10-23
申请号：US12507591
申请日：2009-07-22
申请人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
发明人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
IPC分类号： H05K7/00
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/60 , H01L25/0652 , H01L2224/16225 , H01L2924/10253 , H01L2924/157 , Y02T10/82 , H01L2924/00
摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
摘要翻译：一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片硅载体衬底和设置在硅载体衬底上的时钟芯片。

6. 发明申请

US20120265967A1 IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS 有权
标题翻译：使用非连续寄存器文件指定器实施指令集结构
公开(公告)号：US20120265967A1
公开(公告)日：2012-10-18
申请号：US13425808
申请日：2012-03-21
申请人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30032 , G06F9/30036 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/30181
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理指令集的指令。该指令包括不连续的寄存器说明符。

7. 发明申请

US20090109780A1 HYBRID STATIC AND DYNAMIC SENSING FOR MEMORY ARRAYS 有权
标题翻译：用于存储阵列的混合静态和动态感测
公开(公告)号：US20090109780A1
公开(公告)日：2009-04-30
申请号：US11929875
申请日：2007-10-30
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C11/413
摘要： A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.
摘要翻译：用于存储器的混合电路包括：偏斜静态逻辑门电路; 与静态逻辑门电路相结合的动态预放电装置，用于将静态逻辑门电路作为动态电路进行操作。

8. 发明授权

US07501850B1 Scannable limited switch dynamic logic (LSDL) circuit 失效
标题翻译：可扫描有限开关动态逻辑（LSDL）电路
公开(公告)号：US07501850B1
公开(公告)日：2009-03-10
申请号：US11961548
申请日：2007-12-20
申请人： Anthony Correale, Jr. , Thomas A. Dick , Sven E. Meier , Robert K. Montoye
发明人： Anthony Correale, Jr. , Thomas A. Dick , Sven E. Meier , Robert K. Montoye
IPC分类号： H03K19/00
CPC分类号： H03K19/094 , G01R31/318541
摘要： A scannable limited switch dynamic logic (LSDL) circuit including a data input and a data output, a combinational logic circuit in communication with the data input, a pre-charge circuit in communication with the combinational logic circuit, a footer circuit in communication with the combinational logic, a keeper circuit in communication with the combinational logic circuit and the pre-charge circuit, a scan input connected to the data input, a scan input circuit in communication with the scan input, the combinational logic circuit, the pre-charge circuit, and the keeper circuit, a modified inverter circuit in communication with the combinational logic circuit, the pre-charge circuit, the keeper circuit, and the scan input circuit, a parallel gate circuit in communication with the modified inverter circuit, a series gate circuit in communication with the modified inverter circuit and the parallel gate circuit, a feedback inverter connected between an internal node and a feedback node, and an output buffer connected between the internal node and the data output.
摘要翻译：包括数据输入和数据输出的可扫描有限切换动态逻辑（LSDL）电路，与数据输入通信的组合逻辑电路，与组合逻辑电路通信的预充电电路，与组合逻辑，与组合逻辑电路和预充电电路通信的保持器电路，连接到数据输入的扫描输入，与扫描输入通信的扫描输入电路，组合逻辑电路，预充电电路和保持器电路，与组合逻辑电路，预充电电路，保持器电路和扫描输入电路通信的修改的反相器电路，与修改的反相器电路通信的并行门电路，串联门电路与修改的逆变器电路和并行门电路通信，连接在内部节点和反馈节点之间的反馈反相器，以及连接在内部节点和数据输出之间的输出缓冲器。

9. 发明授权

US07360063B2 Method for SIMD-oriented management of register maps for map-based indirect register-file access 有权
标题翻译：用于基于地图的间接寄存器文件访问的用于面向SIMD管理寄存器映射的方法
公开(公告)号：US07360063B2
公开(公告)日：2008-04-15
申请号：US11366884
申请日：2006-03-02
申请人： Peter G. Capek , Jeffrey H. Derby , Robert K. Montoye
发明人： Peter G. Capek , Jeffrey H. Derby , Robert K. Montoye
IPC分类号： G06F9/35
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/35 , G06F9/384
摘要： A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.
摘要翻译：提供了一种用于管理处理器内基于地图的间接寄存器文件访问的寄存器映射的设施。管理设施包括包括一组映射的寄存器映射，该映射集合的每个映射具有多个映射寄存器。一组实际寄存器由处理器通过地图集的映射条目间接访问。实际寄存器组中实际寄存器的数量大于映射集中映射条目的数量，映射集合的映射条目仅引用任何给定时间的实际寄存器集合的子集。该设施包括通过基于执行单个更新指令来更新该组映射的至少一个映射的多个映射条目来管理对该映射映射集合的多个条目的更新。

10. 发明授权

US07216141B2 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US07216141B2
公开(公告)日：2007-05-08
申请号：US10702992
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

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