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1. 发明申请

US20120014187A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120014187A1
公开(公告)日：2012-01-19
申请号：US13200361
申请日：2011-09-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

2. 发明申请

US20070195609A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20070195609A1
公开(公告)日：2007-08-23
申请号：US11653866
申请日：2007-01-17
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

3. 发明授权

US08339851B2 Non-volatile memory device and method of operation therefor 失效
公开(公告)号：US08339851B2
公开(公告)日：2012-12-25
申请号：US13200361
申请日：2011-09-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

4. 发明授权

US08081509B2 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08081509B2
公开(公告)日：2011-12-20
申请号：US12662571
申请日：2010-04-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器; 并且在阱中形成去耦合晶体管。

5. 发明申请

US20100208526A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100208526A1
公开(公告)日：2010-08-19
申请号：US12662571
申请日：2010-04-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/14
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器; 并且在阱中形成去耦合晶体管。

6. 发明授权

US07733695B2 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07733695B2
公开(公告)日：2010-06-08
申请号：US11653866
申请日：2007-01-17
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

7. 发明申请

US20140211565A1 METHODS OF PROGRAMMING MULTI-LEVEL CELL NONVOLATILE MEMORY DEVICES AND DEVICES SO OPERATING 有权
标题翻译：编程多级细胞非易失性存储器件的方法和操作的器件
公开(公告)号：US20140211565A1
公开(公告)日：2014-07-31
申请号：US14165835
申请日：2014-01-28
申请人： Jung-Ho Song , Su-Yong Kim , Sang-Won Hwang
发明人： Jung-Ho Song , Su-Yong Kim , Sang-Won Hwang
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
摘要： To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.
摘要翻译：在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

8. 发明授权

US08446776B2 Method of programming memory cells for a non-volatile memory device 有权
标题翻译：为非易失性存储器件编程存储器单元的方法
公开(公告)号：US08446776B2
公开(公告)日：2013-05-21
申请号：US13022688
申请日：2011-02-08
申请人： Sang-Won Hwang , Chan-Ho Kim
发明人： Sang-Won Hwang , Chan-Ho Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3454
摘要： A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.
摘要翻译：提供了一种用于非易失性存储器件的存储器单元的编程方法。该方法包括基于编程电压，第一验证电压和第二验证电压来执行增量步进脉冲程序（ISPP）操作，并且基于存储器的第一通过失败结果来改变编程电压的增量值基于第一验证电压产生第一通过失败结果。基于存储单元的第二通过失败结果完成ISPP操作，基于第二验证电压生成第二通过失败结果。

9. 发明授权

US08295092B2 Non-volatile memory device and memory system 失效
标题翻译：非易失性存储器件和存储器系统
公开(公告)号：US08295092B2
公开(公告)日：2012-10-23
申请号：US12498477
申请日：2009-07-07
申请人： Chan-ho Kim , Sang-Won Hwang
发明人： Chan-ho Kim , Sang-Won Hwang
IPC分类号： G11C11/36 , G11C7/00
CPC分类号： G11C16/0483 , G11C7/12 , G11C16/24
摘要： A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.
摘要翻译：非易失性存储器件包括连接到字线并沿行方向布置的多个存储器单元，分别连接到多个存储器单元的位线和位线偏置电路，其被配置为根据位置分别控制提供给位线的偏置电压的存储单元沿着行方向。

10. 发明授权

US07757153B2 Multi-bit memory device and memory system 有权
标题翻译：多位存储器和存储器系统
公开(公告)号：US07757153B2
公开(公告)日：2010-07-13
申请号：US11605977
申请日：2006-11-30
申请人： Sang-Won Hwang , Jong-Soo Lee
发明人： Sang-Won Hwang , Jong-Soo Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C29/42 , G11C29/52 , G11C2029/0409 , G11C2211/5641 , G11C2211/5642
摘要： A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.
摘要翻译：公开了非易失性存储器件，存储器系统和读取方法。存储器件包括存储单元阵列，其包括多个存储器块，每个存储块具有适于存储N位的多个存储器单元，其中N是大于1的整数，被配置为执行适于从存储单元阵列和输出读取数据，错误校正电路，被配置为检测和校正存储在存储块K中的读取数据中的错误并产生相应的错误信息;以及控制电路，被配置为减少存储在多个存储单元阵列中的位数用于存储块K从N到J的存储器单元，其中J是小于N但大于零的整数，其响应于错误信息。

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