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1. 发明授权

US07858482B2 Method of forming a semiconductor device using stress memorization 有权
标题翻译：使用应力记忆形成半导体器件的方法
公开(公告)号：US07858482B2
公开(公告)日：2010-12-28
申请号：US12059286
申请日：2008-03-31
申请人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
发明人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译：应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。然后去除SMT膜。在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

2. 发明申请

US20090242944A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION 有权
标题翻译：使用应力记忆形成半导体器件的方法
公开(公告)号：US20090242944A1
公开(公告)日：2009-10-01
申请号：US12059286
申请日：2008-03-31
申请人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
发明人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译：应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。然后去除SMT膜。在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

3. 发明授权

US06514808B1 Transistor having a high K dielectric and short gate length and method therefor 失效
标题翻译：具有高K电介质和短栅极长度的晶体管及其方法
公开(公告)号：US06514808B1
公开(公告)日：2003-02-04
申请号：US09997358
申请日：2001-11-30
申请人： Srikanth B. Samavedam , Christopher C. Hobbs , William J. Taylor, Jr.
发明人： Srikanth B. Samavedam , Christopher C. Hobbs , William J. Taylor, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/28176 , H01L21/28123 , H01L21/28194 , H01L21/31122 , H01L21/31604 , H01L21/31608 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L21/32135 , H01L29/512 , H01L29/517
摘要： A transistor device (19) utilizes a high K dielectric (24) between a gate electrode (16) and a substrate (12). The high K dielectric (24) is etched under the gate electrode (16) so that there is an area between the gate electrode (16) and the substrate (12) that is void of high K dielectric (24). The source/drains extensions (28 and 30) are minimized to extend substantially in alignment with the edge of gate dielectric (24) to reduce overlap with the gate dielectric (24). This results in reduced capacitance between the gate and the source/drain extensions. The void areas (20 and 22) between the gate and the substrate (12) may remain void or may be filled with a low K dielectric, or at least a dielectric that is not high K.
摘要翻译：晶体管器件（19）利用栅电极（16）和衬底（12）之间的高K电介质（24）。在栅电极（16）下蚀刻高K电介质（24），使得在栅极电极（16）和基板（12）之间存在无K电介质（24）的区域。源极/漏极延伸部（28和30）被最小化以基本上与栅极电介质（24）的边缘对准以减小与栅极电介质（24）的重叠。这导致栅极和源极/漏极延伸部之间的电容降低。栅极和衬底（12）之间的空隙区域（20和22）可以保持空隙，或者可以填充低K电介质，或者至少是不高K的电介质。

4. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

5. 发明授权

US5960270A Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions 失效
标题翻译：用于形成具有在形成自对准源区和漏区之后形成的金属栅电极的MOS晶体管的方法
公开(公告)号：US5960270A
公开(公告)日：1999-09-28
申请号：US907990
申请日：1997-08-11
申请人： Veena Misra , Suresh Venkatesan , Christopher C. Hobbs , Brad Smith , Jeffrey S. Cope , Earnest B. Wilson
发明人： Veena Misra , Suresh Venkatesan , Christopher C. Hobbs , Brad Smith , Jeffrey S. Cope , Earnest B. Wilson
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/768 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/2257 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/66606 , H01L21/76807 , H01L29/4958 , H01L29/4966 , H01L29/4975 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/7833
摘要： A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
摘要翻译：用于形成金属栅极MOS晶体管的方法开始于在衬底（12或102）内形成源极和漏极（26,28和/或118）。这些源极和漏极区域（26,28和118）与光刻图案特征（24或108）自对准。在形成源极和漏极区之后，特征（24和108）被处理以用金属栅极层（28a或128a）填充这些特征，然后将该金属层（28a或128a）化学机械抛光（CMPed）以形成在特征（24或108）内的金属插塞区域（28b或128b），插塞区域（28b或128b）以镶嵌或双重嵌入方式形成，其中该金属插塞区域（28b或128b）是自对准的到先前形成的源极和漏极区，并且优选地用作金属MOS栅极区。

6. 发明授权

US06573160B2 Method of recrystallizing an amorphous region of a semiconductor 有权
标题翻译：重结晶半导体的非晶区域的方法
公开(公告)号：US06573160B2
公开(公告)日：2003-06-03
申请号：US09578404
申请日：2000-05-26
申请人： William J. Taylor, Jr. , Marius Orlowski , David C. Gilmer , Prasad V. Alluri , Christopher C. Hobbs , Michael J. Rendon , Iuval R. Clejan
发明人： William J. Taylor, Jr. , Marius Orlowski , David C. Gilmer , Prasad V. Alluri , Christopher C. Hobbs , Michael J. Rendon , Iuval R. Clejan
IPC分类号： H01L2120
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/2022 , H01L21/823807 , H01L21/823857 , H01L29/517 , H01L29/6659
摘要： Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.
摘要翻译：提出了用于形成覆盖非晶衬底材料的栅介质层（702）的技术。此外，提出了允许在掺杂操作中使用非晶硅的低温处理操作的技术。在形成包括在半导体器件的栅极结构（804）中的结构之前形成非晶硅区域（604,606），其中栅极结构（804）优选地使用允许非晶硅区域（ 604,606）保持在非晶状态。源极/漏极区（1004,1006）形成在非晶硅区（604,606）中，然后将衬底退火以使非晶区重结晶。

7. 发明授权

US06300202B1 Selective removal of a metal oxide dielectric 有权
标题翻译：选择性去除金属氧化物电介质
公开(公告)号：US06300202B1
公开(公告)日：2001-10-09
申请号：US09574732
申请日：2000-05-18
申请人： Christopher C. Hobbs , Rama I. Hegde , Phillip J. Tobin
发明人： Christopher C. Hobbs , Rama I. Hegde , Phillip J. Tobin
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28035 , H01L21/2807 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.
摘要翻译：公开了一种用于形成半导体器件的方法，其中在衬底上形成金属氧化物栅极电介质层。然后在金属氧化物层上形成栅电极，从而暴露金属氧化物层的一部分。然后将金属氧化物栅介质层的暴露部分化学还原成金属或金属氢化物。然后用常规的湿蚀刻或湿/干蚀刻组合去除金属或金属氢化物。金属氧化物层可以包括诸如锆，钽，铪，钛或镧的金属元素，并且还可以包括另外的元素如硅或氮。还原金属氧化物层可以包括在氧气分压下在金属氧化物栅极电介质层中退火，其氧分压小于在给定温度下氧解吸的临界极限。在另一个实施方案中，还原金属氧化物栅极电介质层可以包括使金属氧化物层退火，同时向金属氧化物栅极电介质层供应诸如硅烷，氨，锗烷，氢和肼的含氢前体。栅电极可以包括栅极电极堆叠，其在金属氧化物栅极介电层上方包括氮化钛层，并且在氮化钛层上方包含含硅覆盖层。

8. 发明申请

US20120007052A1 Apparatus, System, and Method for Dual-Channel Nanowire FET Device 失效
标题翻译：双通道纳米线FET器件的装置，系统和方法
公开(公告)号：US20120007052A1
公开(公告)日：2012-01-12
申请号：US12831839
申请日：2010-07-07
申请人： Christopher C. Hobbs , Kerem Akarvardar , Injo OK
发明人： Christopher C. Hobbs , Kerem Akarvardar , Injo OK
IPC分类号： H01L27/092 , H01L29/775 , H01L21/8238
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L27/1211 , H01L29/161 , H01L29/42392 , H01L29/66439 , H01L29/78696
摘要： An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor includes a first group of nanowires made of silicon. The nanowire FET device may also include a second transistor on the same substrate, where the second transistor includes a second group of nanowires made of silicon-germanium.
摘要翻译：提出了一种双通道FET器件的装置，系统和方法。在一些实施例中，纳米线FET器件可以包括衬底上的第一晶体管，其中第一晶体管包括由硅制成的第一组纳米线。纳米线FET器件还可以包括在同一衬底上的第二晶体管，其中第二晶体管包括由硅 - 锗制成的第二组纳米线。

9. 发明授权

US06818493B2 Selective metal oxide removal performed in a reaction chamber in the absence of RF activation 有权
标题翻译：在没有RF激活的情况下在反应室中进行选择性金属氧化物去除
公开(公告)号：US06818493B2
公开(公告)日：2004-11-16
申请号：US09916023
申请日：2001-07-26
申请人： Christopher C. Hobbs , Philip J. Tobin
发明人： Christopher C. Hobbs , Philip J. Tobin
IPC分类号： H01L218238
CPC分类号： H01L29/513 , H01L21/26586 , H01L21/28238 , H01L21/31122 , H01L29/1083 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.
摘要翻译：使用气体HCl（HCl），加热和不存在rf的组合除去用作栅极电介质的金属氧化物。优选氧化铪的金属氧化物在不在栅极下方的区域被有效去除。使用HCl导致不被除去的金属氧化物的界面氧化物。除去界面以除去金属并由另一界面氧化物层代替。因此，随后的植入步骤仅通过界面氧化物而不是通过金属氧化物。因此，避免了通过金属氧化物注入相关的问题。

10. 发明授权

US6004850A Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation 失效
标题翻译：与金属晶体管栅电极集成的氧化钽抗反射涂层（ARC）和形成方法
公开(公告)号：US6004850A
公开(公告)日：1999-12-21
申请号：US28101
申请日：1998-02-23
申请人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
发明人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28194 , H01L21/0276 , H01L21/28079 , H01L21/28123 , H01L21/32137 , H01L29/495 , H01L29/517 , H01L21/28202 , H01L29/518
摘要： A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.
摘要翻译：通过在衬底（20）上形成MOS金属栅电极层（20）开始形成钽基抗反射涂层（ARC）层的方法。 MOS金属栅电极层（20）被ARC层（22）覆盖。 ARC层优选是五氧化二钽或掺杂有一个或多个氮原子和/或硅原子的五氧化二钽层。然后，层（22和20）选择性地被掩蔽的光致抗蚀剂（24），其被选择性地暴露于深紫外（DUV）辐射（28）。 ARC层（22）改善了曝光期间MOS金属栅极的光刻临界尺寸（CD）控制。然后使用氟 - 氯 - 氟时间进行的反应离子蚀刻（RIE）工艺对最终的MOS金属栅极进行构图和蚀刻，由此最终形成金属栅极MOS晶体管。

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