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1. 发明授权

US07858482B2 Method of forming a semiconductor device using stress memorization 有权
标题翻译：使用应力记忆形成半导体器件的方法
公开(公告)号：US07858482B2
公开(公告)日：2010-12-28
申请号：US12059286
申请日：2008-03-31
申请人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
发明人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译：应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。然后去除SMT膜。在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

2. 发明申请

US20090242944A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION 有权
标题翻译：使用应力记忆形成半导体器件的方法
公开(公告)号：US20090242944A1
公开(公告)日：2009-10-01
申请号：US12059286
申请日：2008-03-31
申请人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
发明人： Da Zhang , Christopher C. Hobbs , Srikanth B. Samavedam
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译：应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。然后去除SMT膜。在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

3. 发明申请

US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices 有权
标题翻译： CMOS工艺与优化的PMOS和NMOS晶体管器件
公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

4. 发明授权

US08003454B2 CMOS process with optimized PMOS and NMOS transistor devices 有权
标题翻译： CMOS工艺具有优化的PMOS和NMOS晶体管器件
公开(公告)号：US08003454B2
公开(公告)日：2011-08-23
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

5. 发明申请

US20090289280A1 Method for Making Transistors and the Device Thereof 审中-公开
标题翻译：制造晶体管及其器件的方法
公开(公告)号：US20090289280A1
公开(公告)日：2009-11-26
申请号：US12125853
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

6. 发明授权

US08643217B2 Apparatus and method for boosting output of a generator set 有权
标题翻译：一种用于提升发电机组输出的装置和方法
公开(公告)号：US08643217B2
公开(公告)日：2014-02-04
申请号：US12674936
申请日：2007-12-26
申请人： Thomas Gietzold , Jeffrey J. Burchill , Da Zhang , Weiqian Hu
发明人： Thomas Gietzold , Jeffrey J. Burchill , Da Zhang , Weiqian Hu
IPC分类号： H02J3/00
CPC分类号： H02P9/02 , Y10T307/675
摘要： An apparatus and method for boosting output of a generator set are provided. The output of the generator set is connected to an electrical load. The apparatus includes an energy storage unit, and a power-electronic unit. The energy storage unit uses batteries and capacitors to store electric energy. The power-electronic unit measures an electrical parameter of the output of the generator set. Based on the measured electrical parameter and a predefined criterion, the power-electronic unit determines additional energy required by the electrical load. Thereafter, the power-electronic unit supplies the additional energy to the electrical load. The additional energy is drawn from the energy storage unit.
摘要翻译：提供了一种用于提升发电机组的输出的装置和方法。发电机组的输出连接到电气负载。该装置包括能量存储单元和电力电子单元。储能单元使用电池和电容器来储存电能。电力电子单元测量发电机组输出的电气参数。基于测量的电参数和预定标准，功率电子单元确定电负载所需的附加能量。此后，电力电子单元向电负载提供额外的能量。额外的能量从能量存储单元中抽出。

7. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

8. 发明授权

US07795089B2 Forming a semiconductor device having epitaxially grown source and drain regions 有权
标题翻译：形成具有外延生长的源区和漏区的半导体器件
公开(公告)号：US07795089B2
公开(公告)日：2010-09-14
申请号：US11680219
申请日：2007-02-28
申请人： Laegu Kang , Vishal P. Trivedi , Da Zhang
发明人： Laegu Kang , Vishal P. Trivedi , Da Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66772
摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.
摘要翻译：在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。在第一和第二区域上形成第一绝缘层。第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。在凹部中外延生长半导体材料。去除第一绝缘层的剩余部分。

9. 发明申请

US20100078687A1 Method for Transistor Fabrication with Optimized Performance 有权
标题翻译：具有优化性能的晶体管制造方法
公开(公告)号：US20100078687A1
公开(公告)日：2010-04-01
申请号：US12242078
申请日：2008-09-30
申请人： Da Zhang , Voon-Yew Thean , Christopher V. Baiocco , Jie Chen , Weipeng Li , Young Way Teh , Jin Wallner
发明人： Da Zhang , Voon-Yew Thean , Christopher V. Baiocco , Jie Chen , Weipeng Li , Young Way Teh , Jin Wallner
IPC分类号： H01L21/8238 , H01L29/04
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/517 , H01L29/6653 , H01L29/7843
摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
摘要翻译：一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72）结构（26,36）和拉伸侧壁间隔物（62）。在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94）栅极结构（26,36）和侧壁间隔物（92）。

10. 发明授权

US07538002B2 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效
标题翻译：集成源极/漏极应力和半导体介电层应力的半导体工艺
公开(公告)号：US07538002B2
公开(公告)日：2009-05-26
申请号：US11361171
申请日：2006-02-24
申请人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
发明人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译：半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

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