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1. 发明授权

US06187679B1 Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US06187679B1
公开(公告)日：2001-02-13
申请号：US08807739
申请日：1997-02-26
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： H01L2144
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

2. 发明授权

US5828131A Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US5828131A
公开(公告)日：1998-10-27
申请号：US586046
申请日：1996-01-16
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： C23C20/02 , C30B1/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

3. 发明授权

US06215190B1 Borderless contact to diffusion with respect to gate conductor and methods for fabricating 失效
标题翻译：与栅极导体无关的扩散接触和制造方法
公开(公告)号：US06215190B1
公开(公告)日：2001-04-10
申请号：US09076525
申请日：1998-05-12
申请人： James Allen Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Prxarik , Kirk David Peterson , Jed Hickory Rankin
发明人： James Allen Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Prxarik , Kirk David Peterson , Jed Hickory Rankin
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76888 , H01L27/11
摘要： A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.
摘要翻译：通过采用双重绝缘薄膜叠层作为掩模，提供了一种无边界的相对于栅极导体的扩散接触，用于限定整个芯片的栅极导体形状，并在限定栅极导体形状之后在暴露的导电层上提供相对较薄的损伤防止层。在一个实施例中，通过在衬底上形成绝缘层来提供无边界接触，在绝缘层上提供导电层，在导电层上提供第二绝缘层，在第二绝缘层上提供第三绝缘层，去除预选第二绝缘层和第三绝缘层的部分，在去除第二和第三绝缘层的那些区域中提供防损害层，去除第三绝缘层的预选部分，去除损坏防止层，去除导电层的暴露部分并且去除第二绝缘层的现在暴露部分。

4. 发明授权

US06498096B2 Borderless contact to diffusion with respect to gate conductor and methods for fabricating 失效
标题翻译：与栅极导体无关的扩散接触和制造方法
公开(公告)号：US06498096B2
公开(公告)日：2002-12-24
申请号：US09800911
申请日：2001-03-08
申请人： James Allan Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Pekarik , Kirk David Peterson , Jed Hickory Rankin
发明人： James Allan Bruce , Jonathan Daniel Chapple-Sokol , Charles W. Koburger, III , Michael James Lercel , Randy William Mann , James Spiros Nakos , John Joseph Pekarik , Kirk David Peterson , Jed Hickory Rankin
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76888 , H01L27/11
摘要： A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.
摘要翻译：通过采用双重绝缘薄膜叠层作为掩模，提供了一种无边界的相对于栅极导体的扩散接触，用于限定整个芯片的栅极导体形状，并在限定栅极导体形状之后在暴露的导电层上提供相对较薄的损伤防止层。在一个实施例中，通过在衬底上形成绝缘层来提供无边界接触，在绝缘层上提供导电层，在导电层上提供第二绝缘层，在第二绝缘层上提供第三绝缘层，去除预选第二绝缘层和第三绝缘层的部分，在去除第二和第三绝缘层的那些区域中提供防损害层，去除第三绝缘层的预选部分，去除损坏防止层，去除导电层的暴露部分并且去除第二绝缘层的现在暴露部分。

5. 发明授权

US5675185A Semiconductor structure incorporating thin film transistors with undoped cap oxide layers 失效
标题翻译：结合具有未掺杂的帽氧化物层的薄膜晶体管的半导体结构
公开(公告)号：US5675185A
公开(公告)日：1997-10-07
申请号：US537219
申请日：1995-09-29
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

6. 发明授权

US07745863B2 Flip FERAM cell and method to form same 失效
标题翻译：翻转FERAM细胞和方法形成相同
公开(公告)号：US07745863B2
公开(公告)日：2010-06-29
申请号：US12146576
申请日：2008-06-26
申请人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29/82
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

7. 发明申请

US20080124880A1 FET STRUCTURE USING DISPOSABLE SPACER AND STRESS INDUCING LAYER 审中-公开
标题翻译：使用可分散间隔器和应力诱导层的FET结构
公开(公告)号：US20080124880A1
公开(公告)日：2008-05-29
申请号：US11534651
申请日：2006-09-23
申请人： Wenhe Lin , Randy William Mann , Padraic C. Shafer , Christopher Vincent Baiocco , Zhijoing Luo , Haining S. Yang , Xiangdong Chen
发明人： Wenhe Lin , Randy William Mann , Padraic C. Shafer , Christopher Vincent Baiocco , Zhijoing Luo , Haining S. Yang , Xiangdong Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.
摘要翻译：一些非限制性示例性实施例包括一次性间隔物形成和移除过程以及应力覆盖层过程。我们在衬底上提供栅极结构。我们形成邻接至少一个栅极侧壁的一次性间隔物。我们在一次性间隔物附近形成S / D区域。我们取出一次性垫片。我们可以在S / D和门上形成硅化物区域。在一方面，我们可以在邻近栅极的基板的栅极和表面部分上沉积应力诱导层，其中应力诱导衬垫向栅电极下方的衬底的一部分提供应力。

8. 发明授权

US06774017B2 Method and structures for dual depth oxygen layers in silicon-on-insulator processes 有权
标题翻译：硅绝缘体工艺中双重深度氧层的方法和结构
公开(公告)号：US06774017B2
公开(公告)日：2004-08-10
申请号：US10190405
申请日：2002-07-03
申请人： Jeffrey Scott Brown , Andres Bryant , Robert J. Gauthier, Jr. , Randy William Mann , Steven Howard Voldman
发明人： Jeffrey Scott Brown , Andres Bryant , Robert J. Gauthier, Jr. , Randy William Mann , Steven Howard Voldman
IPC分类号： H01L2120
CPC分类号： H01L27/1203 , H01L21/26533 , H01L21/76232 , H01L21/76264 , H01L21/76267 , H01L21/76283
摘要： A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.
摘要翻译：一种半导体结构及其相关制造方法，包括具有连续掩埋氧化物层并具有多个沟槽隔离结构的衬底。掩埋氧化物层可以位于衬底内的多于一个深度处。沟槽隔离结构的几何形状可随深度而变化。沟槽隔离结构可以接触或不接触埋入的氧化物层。两个沟槽隔离结构可以将衬底穿透到相同的深度或不同的深度。沟槽隔离结构在衬底内的区域之间提供绝缘分离，并且分离的区域可以包含半导体器件。半导体结构便于在公共晶片上提供数字和模拟器件。双深埋入氧化物层有利于非对称半导体结构。

9. 发明授权

US06614124B1 Simple 4T static ram cell for low power CMOS applications 失效
标题翻译：用于低功耗CMOS应用的简单4T静态柱塞电池
公开(公告)号：US06614124B1
公开(公告)日：2003-09-02
申请号：US09724083
申请日：2000-11-28
申请人： Jeffrey Scott Brown , Chung Hon Lam , Randy William Mann
发明人： Jeffrey Scott Brown , Chung Hon Lam , Randy William Mann
IPC分类号： H01L2711
CPC分类号： G11C11/412 , H01L27/11
摘要： An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.
摘要翻译： SRAM存储单元器件包括字线和位线输入，用于使得能够对存储单元内容进行读/写访问;以及扩散区，用于在不访问单元时保持电压以保持存储单元内容。该器件还包括具有栅极输入的晶体管器件，用于在不执行存储器单元读/写访问时接收字线电压以截止晶体管器件; 以及当栅极电压施加到栅极输入并且晶体管器件截止时，形成在晶体管器件栅极下方的用于泄漏电流的电阻性能的栅极氧化层。扩散区域接收从施加到所述栅极输入端的字线电压导出的电压，以便在没有施加的位线电压的情况下保持所述存储单元的内容从而降低功耗。

10. 发明授权

US5672901A Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits 失效
标题翻译：用于在集成电路的半导体衬底上互连不同多晶硅区的结构
公开(公告)号：US5672901A
公开(公告)日：1997-09-30
申请号：US702863
申请日：1996-08-26
申请人： John Robert Abernathey , Randy William Mann , Paul Christian Parries , Julie Anne Springer
发明人： John Robert Abernathey , Randy William Mann , Paul Christian Parries , Julie Anne Springer
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/535
CPC分类号： H01L21/768 , H01L21/76895 , H01L23/53271 , H01L2924/0002
摘要： A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.
摘要翻译：提供了形成集成电路器件的互连的方法，特别是互连间隔开的源极/漏极区域和/或栅极区域以及所得到的结构。诸如二氧化硅的蚀刻停止材料沉积在其上形成器件的整个衬底上。一层硅沉积在蚀刻停止材料上，并且硅被选择性地蚀刻以在要连接的区域上露出蚀刻停止材料。然后去除那些区域处的蚀刻停止材料。此后，在连接间隔开的区域的基板上形成高导电性材料，其是由硅层和难熔金属形成的难熔金属或硅化物。

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