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1. 发明授权

US5675185A Semiconductor structure incorporating thin film transistors with undoped cap oxide layers 失效
标题翻译：结合具有未掺杂的帽氧化物层的薄膜晶体管的半导体结构
公开(公告)号：US5675185A
公开(公告)日：1997-10-07
申请号：US537219
申请日：1995-09-29
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Bret Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

2. 发明授权

US6022766A Semiconductor structure incorporating thin film transistors, and methods for its manufacture 失效
标题翻译：掺入薄膜晶体管的半导体结构及其制造方法
公开(公告)号：US6022766A
公开(公告)日：2000-02-08
申请号：US797904
申请日：1997-02-10
申请人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Brett Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
发明人： Bomy Able Chen , Subhash Balakrishna Kulkarni , Jerome Brett Lasky , Randy William Mann , Edward Joseph Nowak , Werner Alois Rausch , Francis Roger White
IPC分类号： H01L27/06 , H01L27/11 , H01L21/00
CPC分类号： H01L27/1108 , H01L27/0688 , H01L2924/0002
摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.
摘要翻译：公开了一种改进的场效应晶体管（FET）结构。它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。还公开了相关过程。

3. 发明授权

US08586488B2 Configuring radiation sources to simultaneously irradiate a substrate 失效
标题翻译：配置辐射源同时照射基板
公开(公告)号：US08586488B2
公开(公告)日：2013-11-19
申请号：US12860990
申请日：2010-08-23
申请人： Brent Alan Anderson , Edward Joseph Nowak
发明人： Brent Alan Anderson , Edward Joseph Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/268
摘要： A computer program product and system for configuring J electromagnetic radiation sources (J≧2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1−S1|, |W2−S2|, |WI−SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
摘要翻译：一种用于配置J电磁辐射源（J> = 2）以同时照射衬底的计算机程序产品和系统。每个源具有不同的发射辐射的波长和角分布的功能。衬底包括基层，I堆叠（I> = 2）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。为了将I堆叠同时暴露于来自J源的辐射，计算Pj，使得误差E是| W1-S1 |，| W2-S2 |，| WI-SI |的函数; 相对于Pj（j = 1，...，J）被最小化。 Wi和Si分别表示通过堆叠i（i = 1，...，I）传输到衬底中的实际和目标能量通量。这些堆叠暴露于由所计算的Pj（j = 1，...，J）表征的源的辐射。

4. 发明授权

US07399664B1 Formation of spacers for FinFETs (Field Effect Transistors) 有权
标题翻译： FinFET间隔物的形成（场效应晶体管）
公开(公告)号：US07399664B1
公开(公告)日：2008-07-15
申请号：US11679862
申请日：2007-02-28
申请人： Brent Alan Anderson , Edward Joseph Nowak , Kathryn Turner Schonenberg
发明人： Brent Alan Anderson , Edward Joseph Nowak , Kathryn Turner Schonenberg
IPC分类号： H01L21/84 , H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/4763 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66795
摘要： A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.
摘要翻译：一种结构及其形成方法。该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域半导体鳍片区域的侧壁。栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。半导体鳍片区域的第一侧壁暴露于周围环境。第一间隔区域的顶表面与栅电极区域的顶表面共面。

5. 发明申请

US20080157188A1 FIELD EFFECT TRANSISTOR WITH THIN GATE ELECTRODE AND METHOD OF FABRICATING SAME 有权
标题翻译：具有薄门电极的场效应晶体管及其制造方法
公开(公告)号：US20080157188A1
公开(公告)日：2008-07-03
申请号：US12037121
申请日：2008-02-26
申请人： Brent Alan Anderson , Andres Bryant , William F. Clark , Edward Joseph Nowak
发明人： Brent Alan Anderson , Andres Bryant , William F. Clark , Edward Joseph Nowak
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度厚度。

6. 发明授权

US07374980B2 Field effect transistor with thin gate electrode and method of fabricating same 有权
标题翻译：具有薄栅电极的场效应晶体管及其制造方法
公开(公告)号：US07374980B2
公开(公告)日：2008-05-20
申请号：US11549311
申请日：2006-10-13
申请人： Brent Alan Anderson , Andres Bryant , William F. Clark, Jr. , Edward Joseph Nowak
发明人： Brent Alan Anderson , Andres Bryant , William F. Clark, Jr. , Edward Joseph Nowak
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度厚度。

7. 发明授权

US07323374B2 Dense chevron finFET and method of manufacturing same 有权
标题翻译：密集人字形finFET及其制造方法
公开(公告)号：US07323374B2
公开(公告)日：2008-01-29
申请号：US11162663
申请日：2005-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

8. 发明授权

US06891235B1 FET with T-shaped gate 有权
标题翻译：带T形门的FET
公开(公告)号：US06891235B1
公开(公告)日：2005-05-10
申请号：US09713830
申请日：2000-11-15
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Edward Joseph Nowak
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Edward Joseph Nowak
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L21/28123 , H01L29/1045 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/7833
摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.
摘要翻译： FET具有T形栅极。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。两层被图案化在一起。然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。在另一个实施例中，栅极由单个栅极导体形成。金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。蚀刻硅化物以提供凹口。

9. 发明授权

US06365484B1 Method of forming semiconductor device with decoupling capacitance 失效
标题翻译：用去耦电容形成半导体器件的方法
公开(公告)号：US06365484B1
公开(公告)日：2002-04-02
申请号：US09634970
申请日：2000-08-09
申请人： Edward Joseph Nowak , Minh Ho Tong
发明人： Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2120
CPC分类号： H01L27/1203 , H01L27/0248 , H01L27/088
摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.
摘要翻译：公开了提供一种去耦电容的半导体器件及其方法。半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

10. 发明申请

US20100318210A1 CONFIGURING RADIATION SOURCES TO SIMULTANEOUSLY IRRADIATE A SUBSTRATE 失效
标题翻译：配置辐射源同时辐射基板
公开(公告)号：US20100318210A1
公开(公告)日：2010-12-16
申请号：US12860990
申请日：2010-08-23
申请人： Brent Alan Anderson , Edward Joseph Nowak
发明人： Brent Alan Anderson , Edward Joseph Nowak
IPC分类号： G06F17/00
CPC分类号： H01L21/268
摘要： A computer program product and system for configuring J electromagnetic radiation sources (J≧2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1−S1|, |W2−S2|, |WI−SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
摘要翻译：一种用于配置J电磁辐射源（J≥2）以同时照射衬底的计算机程序产品和系统。每个源具有不同的发射辐射的波长和角分布的功能。基板包括基层和I堆叠（I≥2）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。为了将I堆叠同时暴露于来自J源的辐射，计算Pj，使得误差E是| W1-S1 |，| W2-S2 |，| WI-SI |的函数; 相对于Pj（j = 1，...，J）被最小化。 Wi和Si分别表示通过堆叠i（i = 1，...，I）传输到衬底中的实际和目标能量通量。这些堆叠暴露于由所计算的Pj（j = 1，...，J）表征的源的辐射。

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