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1. 发明授权

US06933743B2 Dual mode analog differential and CMOS logic circuit 有权
标题翻译：双模式模拟差分和CMOS逻辑电路
公开(公告)号：US06933743B2
公开(公告)日：2005-08-23
申请号：US10718219
申请日：2003-11-20
申请人： Delbert R. Cecchi , Michael Launsbach , Curtis Walter Preuss , David W. Siljenberg
发明人： Delbert R. Cecchi , Michael Launsbach , Curtis Walter Preuss , David W. Siljenberg
IPC分类号： G01R31/3167 , G01R31/317 , H03K19/094 , H03K19/00
CPC分类号： H03K19/09432 , G01R31/3167 , G01R31/31701
摘要： A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.
摘要翻译：提供了双模式，模拟差分和互补金属氧化物半导体（CMOS）逻辑电路。该电路包括用于接收差分输入信号的差分输入。开关对耦合到差分输入。耦合到开关对的一对负载电阻器限定用于提供差分输出信号的差分输出。电流源耦合到开关对。控制输入接收控制信号，并且耦合到控制输入的控制电路禁用电流源以响应于被激活的控制信号来选择CMOS测试模式。

2. 发明授权

US06944099B1 Precise time period measurement 失效
标题翻译：精确的时间段测量
公开(公告)号：US06944099B1
公开(公告)日：2005-09-13
申请号：US10865249
申请日：2004-06-10
申请人： Curtis Walter Preuss , Michael Launsbach
发明人： Curtis Walter Preuss , Michael Launsbach
IPC分类号： G01R23/02 , G04F8/00 , G04F10/00
CPC分类号： G04F10/005
摘要： Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit are output that determine the integer and fractional number of the high speed oscillating clock periods which occurred during one reference clock cycle. The measurements are very accurate and all cycles of the reference clock are measured. Such measurements enable various frequency control schemes over the high speed oscillating clock source.
摘要翻译：在诸如压控振荡器（VCO）的高速振荡时钟方面测量相对较慢而精确的参考时钟的周期。已知参考时钟是准确和稳定的，输出时间测量单元的值，其确定在一个参考时钟周期期间发生的高速振荡时钟周期的整数和分数。测量非常精确，并测量参考时钟的所有周期。这种测量使得能够在高速振荡时钟源上实现各种频率控制方案。

3. 发明授权

US06304106B1 CMOS bi-directional current mode differential link with precompensation 有权
标题翻译： CMOS双向电流模式差分链路，带预补偿
公开(公告)号：US06304106B1
公开(公告)日：2001-10-16
申请号：US09506754
申请日：2000-02-18
申请人： Delbert Raymond Cecchi , Charles C. Hanson , Curtis Walter Preuss
发明人： Delbert Raymond Cecchi , Charles C. Hanson , Curtis Walter Preuss
IPC分类号： H03K19094
CPC分类号： H04L25/08
摘要： A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation. The output current of the CMOS driver is a function of a data bit and at least one previous data bit.
摘要翻译：提供了具有预补偿的互补金属氧化物半导体（CMOS）电流模式差分链路。具有预补偿的互补金属氧化物半导体（CMOS）双向电流模式差分链路包括接收数据输入并具有耦合到传输线的输出的CMOS驱动器。 CMOS复制驱动器接收数据输入并提供基本上等于CMOS驱动器输出的复制驱动器输出。 CMOS接收器耦合到传输线和副本驱动器输出。 CMOS接收器从传输线上的信号中减去副本驱动器输出。 CMOS驱动器和CMOS复制驱动器包括多个并联电流源。每个电流源被布置成响应于所施加的控制信号而通过负载发送正或负电流。使用多个并联电流源允许CMOS驱动器有效地实现预补偿。 CMOS驱动器的输出电流是数据位和至少一个先前的数据位的函数。

4. 发明授权

US06603348B1 Center tap level control for current mode differential driver 失效
标题翻译：当前模式差分驱动器的中心抽头级别控制
公开(公告)号：US06603348B1
公开(公告)日：2003-08-05
申请号：US10124966
申请日：2002-04-18
申请人： Curtis Walter Preuss , Charles C. Hanson
发明人： Curtis Walter Preuss , Charles C. Hanson
IPC分类号： G06G712
CPC分类号： H03F3/45179 , H03F2203/45008 , H04L25/0274 , H04L25/0282
摘要： A feedback mechanism is provided to a current mode differential driver by connecting the center tap of a terminator of the output of the driver through feedback resistors to the gates of a positive and a negative current source connected to the driver. Connecting the center tap between the feedback resistors, the average common mode voltage at the output of the differential driver is substantially constant which avoids variations and reflective noise in high speed data transmission that can occur because of manufacturing tolerances.
摘要翻译：通过将驱动器的输出的终端器的中心抽头通过反馈电阻器连接到连接到驱动器的正电流源和负电流源的门，将反馈机制提供给电流模式差分驱动器。连接反馈电阻之间的中心抽头，差分驱动器输出端的平均共模电压基本上是恒定的，避免了由于制造公差而可能发生的高速数据传输中的变化和反射噪声。

5. 发明授权

US5949249A Driver having inductance-controlled current slew rate 失效
标题翻译：驱动器具有电感控制电流转换速率
公开(公告)号：US5949249A
公开(公告)日：1999-09-07
申请号：US838572
申请日：1997-04-10
申请人： Curtis Walter Preuss , Robert Russell Williams
发明人： Curtis Walter Preuss , Robert Russell Williams
IPC分类号： H03K17/16
CPC分类号： H03K17/166
摘要： A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level. A controller responsive to the comparator is provided for controlling the driver to increase and decrease the voltage slew rate at the output device gate when the comparator signal indicates that the current slew rate respectively falls below and exceeds the desired level, thereby controlling the current slew rate through the inductor and through the output device.
摘要翻译：提供一种用于通过使用电感来最小化和控制输出装置的电流转换速率以直接测量当前转换速率的控制系统。例如，控制系统可以用于通过信号驱动器来控制和最小化电流转换速率，并且允许集成电路芯片上的更快的驱动器和/或更大数量的驱动器。根据本发明的一个实施例，电感器与输出装置串联耦合。预驱动器耦合到输出装置的栅极，以在输出装置门处提供电压转换速率。比较器耦合到电感器，用于感测指示通过电感器的电流转换速率的电压，并输出指示电流转换速率是否超过或低于期望电平的信号。提供响应于比较器的控制器，用于当比较器信号指示电流转换速率分别低于并超过期望电平时控制驱动器增加和降低输出器件栅极处的电压转换速率，由此控制电流转换速率通过电感和通过输出装置。

6. 发明授权

US5666354A CMOS bi-directional differential link 失效
标题翻译： CMOS双向差分链路
公开(公告)号：US5666354A
公开(公告)日：1997-09-09
申请号：US575827
申请日：1995-12-20
申请人： Delbert Raymond Cecchi , Curtis Walter Preuss , Donald Joseph Schulte
发明人： Delbert Raymond Cecchi , Curtis Walter Preuss , Donald Joseph Schulte
IPC分类号： H04L5/14 , H04B1/56
CPC分类号： H04L5/1423
摘要： A full-duplex, differential, bi-directional communications link for simultaneously transmitting differential data between electronic devices is provided. Each transceiver coupled to the communications channel comprises a CMOS (Complementary Metal-Oxide Semiconductor) differential driver and receiver. The differential driver provides constant CMOS voltage sources for providing stable data signal transmission at reduced voltage levels. Voltage sources providing a data signal voltage different from the desired data signal voltage can be placed into a high impedance mode to allow the desired data signal voltage to be transmitted on the common line. The differential receiver includes self-biasing feedback circuitry to provide biasing voltages to the circuit while avoiding manufacturing difficulties associated with providing precise bias voltages. The complementary amplifier structure of the receiver provides an increased common mode noise tolerance. The receiver further includes signal separation circuitry to separate the desired recipient signals on the communications channel from those signals which are driven to another differential receiver.
摘要翻译：提供了用于在电子设备之间同时发送差分数据的全双工，差分双向通信链路。耦合到通信信道的每个收发器包括CMOS（互补金属氧化物半导体）差分驱动器和接收器。差分驱动器提供恒定的CMOS电压源，用于在降低的电压电平下提供稳定的数据信号传输。可以将提供不同于所需数据信号电压的数据信号电压的电压源置于高阻抗模式，以允许在公共线路上传输所需的数据信号电压。差分接收器包括自偏置反馈电路以向电路提供偏置电压，同时避免与提供精确偏置电压相关的制造困难。接收器的互补放大器结构提供增加的共模噪声容限。接收机还包括信号分离电路，用于将通信信道上的所需接收信号与被驱动到另一差分接收机的信号分离。

7. 发明授权

US06989709B2 CMOS low voltage high-speed differential amplifier 有权
公开(公告)号：US06989709B2
公开(公告)日：2006-01-24
申请号：US09903239
申请日：2001-07-11
申请人： Delbert Raymond Cecchi , Charles C. Hansen , Curtis Walter Preuss
发明人： Delbert Raymond Cecchi , Charles C. Hansen , Curtis Walter Preuss
IPC分类号： G06G7/26
CPC分类号： H03F3/4521
摘要： A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

8. 发明授权

US06944239B2 CMOS receiver for simultaneous bi-directional links 失效
标题翻译： CMOS接收机用于同时双向链路
公开(公告)号：US06944239B2
公开(公告)日：2005-09-13
申请号：US10037537
申请日：2002-01-02
申请人： Delbert Raymond Cecchi , Charles C. Hanson , Curtis Walter Preuss
发明人： Delbert Raymond Cecchi , Charles C. Hanson , Curtis Walter Preuss
IPC分类号： H04L5/14 , H04L25/02 , H04L25/08 , H04L27/38
CPC分类号： H04L25/0294 , H04L5/1423 , H04L25/0272 , H04L25/0276 , H04L25/0282 , H04L25/085
摘要： Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.
摘要翻译：提供了用于实现能够在同时双向电流模式差分链路中接收信号的接收机的方法和装置。接收机包括电阻求和网络和差分放大器。电阻求和网络还可以包括用于衰减差分放大器处的高频噪声的电容器。高频噪声可能来自信号路径中的阻抗不连续性或数据驱动器与链路中副本驱动器之间的上升或下降转换时间的差异。

9. 发明授权

US06605997B1 CMOS dual-stage differential receiver-amplifer 失效
标题翻译： CMOS双级差分接收放大器
公开(公告)号：US06605997B1
公开(公告)日：2003-08-12
申请号：US10071170
申请日：2002-02-08
申请人： Charles C. Hanson , Curtis Walter Preuss
发明人： Charles C. Hanson , Curtis Walter Preuss
IPC分类号： H03F345
CPC分类号： H03F3/45475 , H03F3/4521
摘要： A differential receiver-amplifier having reduced input distortion at differential input (positive and negative) terminals to the differential receiver-amplifier. The output from the differential receiver-amplifier is generated from a differential signal detector receiving each differential input from one of a pair of differential amplifiers. While each of the differential amplifiers have two differential input terminals of substantially different input impedances, the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier are coupled to the differential positive terminal, and the second differential input terminal of the first differential amplifier and the first differential input terminal of the second differential amplifier are coupled to the differential negative terminal, wherein the resulting input impedance at the differential positive terminal is substantially equal to the resulting input impedance at the differential negative terminal.
摘要翻译：差分接收放大器在差分输入（正极和负极）端子到差分接收放大器的输入失真减小。来自差分接收放大器的输出从接收来自一对差分放大器之一的每个差分输入的差分信号检测器产生。虽然每个差分放大器具有两个基本上不同的输入阻抗的差分输入端子，但是第一差分放大器的第一差分输入端和第二差分放大器的第二差分输入端耦合到差分正极端子，而第二差分放大器第一差分放大器的输入端和第二差分放大器的第一差分输入端耦合到差分负极，其中差分正端子处的所得输入阻抗基本上等于差分负端子处的所得输入阻抗。

10. 发明授权

US5787094A Test and diagnostics for a self-timed parallel interface 失效
标题翻译：自定时并行接口的测试和诊断
公开(公告)号：US5787094A
公开(公告)日：1998-07-28
申请号：US656950
申请日：1996-06-06
申请人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
发明人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
IPC分类号： G06F11/263 , G06F11/267 , G06F11/10 , H03M13/00
CPC分类号： G06F11/221 , G01R31/318385 , G06F11/263
摘要： A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.
摘要翻译：可以测试以系统速度运行的自定时并行接口的方法和装置。提供输出级用于排队测试分组并将测试分组提供给输入级。分组包含数据比特流和诸如循环冗余校验码的错误检测码。输入级耦合到输出级并接收测试数据包以确定数据位流的正确性。在输入级上，错误检测码验证器重新计算错误检测码，并将重新计算的错误检测码与附加到数据比特流的错误检测码进行比较，以确定数据比特流的正确性。输出队列具有用于从接口上的驱动器接收数据的第一输入端口和用于接收伪随机数据位流的第二输入端口。伪随机数据生成器生成伪随机数据比特流。可以根据预定协议对数据比特流进行分组化。可以将输出级的片外信号提供给输入级的输入，以产生片外数据的片上拷贝。

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