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1. 发明授权

US08949493B1 Configurable multi-lane scrambler for flexible protocol support 有权
标题翻译：可配置的多通道加扰器，用于灵活的协议支持
公开(公告)号：US08949493B1
公开(公告)日：2015-02-03
申请号：US12847761
申请日：2010-07-30
申请人： Curt Wortman , Chong H. Lee , Huy Ngo
发明人： Curt Wortman , Chong H. Lee , Huy Ngo
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F13/12 , G06M3/00 , G11C19/00 , G01R31/28 , G06F17/50 , G06F1/02 , G06F7/58 , H04L9/00
CPC分类号： H04L25/03866 , G06F3/00 , G06F5/00 , G06F7/58 , G06F13/00 , G06F13/12 , G06F13/40 , G06F13/4221 , G06F13/4282 , G11C7/1012 , G11C7/1036 , G11C19/00 , G11C19/285 , H04L9/00
摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
摘要翻译：公开了与可配置加扰电路相关的各种结构和方法。实施例可以被配置为支持多个协议中的一个。一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。一些实施例可配置为选择加扰器类型。一些实施例可配置为适应多个协议特定的加扰多项式之一。一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

2. 发明申请

US20100277201A1 EMBEDDED DIGITAL IP STRIP CHIP 审中-公开
标题翻译：嵌入式数字IP条带芯片
公开(公告)号：US20100277201A1
公开(公告)日：2010-11-04
申请号：US12434606
申请日：2009-05-01
申请人： Curt Wortman , Chong H. Lee , Richard G. Cliff
发明人： Curt Wortman , Chong H. Lee , Richard G. Cliff
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84 , H03K19/17724 , H03K19/17732
摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.
摘要翻译：提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。第二区包括标准逻辑单元和基本单元。在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。在一个实施例中，第二区域可以嵌入第一区域。在另一个实施例中，第二区域围绕第一区域的周边限定。可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用40G / 100G替换用于基于计算的应用的诸如PCI Express的原始功能以太网和因特拉肯，用于有线应用。还提供了一种设计集成电路的方法。

3. 发明申请

US20100215086A1 Multi-protocol channel-aggregated configurable transceiver in an integrated circuit 有权
标题翻译：集成电路中的多协议通道聚合可配置收发器
公开(公告)号：US20100215086A1
公开(公告)日：2010-08-26
申请号：US12288178
申请日：2008-10-17
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
IPC分类号： H04B1/38
CPC分类号： H04B1/005 , G06F13/385 , H04L69/12 , H04L69/18
摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
摘要翻译：本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路从属（“PMD”）子层电路。

4. 发明授权

US09531646B1 Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权
标题翻译：多协议可配置收发器，包括集成电路中的可配置的偏移校正
公开(公告)号：US09531646B1
公开(公告)日：2016-12-27
申请号：US12632744
申请日：2009-12-07
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
IPC分类号： G06F3/00 , H04L12/861 , G06F5/10
CPC分类号： H04L49/90 , G06F5/10
摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
摘要翻译：实施例包括可配置的多协议收发器，包括可配置的偏移电路。在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。

5. 发明授权

US08458383B1 Flexible interface for stacked protocol in a programmable integrated circuit device 有权
标题翻译：可编程集成电路器件中堆叠协议的灵活接口
公开(公告)号：US08458383B1
公开(公告)日：2013-06-04
申请号：US11848016
申请日：2007-08-30
申请人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
发明人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
IPC分类号： G06F13/14 , G06F15/16
CPC分类号： G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.
摘要翻译：在可编程设备上，用于具有包括至少物理层，数据链路层和事务层的协议栈的协议的可编程接口的每层可选择地旁路。当旁路一层时，该层下游的所有其他层也被旁路。此外，该接口可以被划分为以不同的时钟速率运行的不同的时钟域，反映了可编程器件内部和可编程器件外部的时钟速率。可以绕过图层以允许用户替换可编程逻辑中的自定义层，或者替换更新的层进行调试。

6. 发明授权

US08165191B2 Multi-protocol channel-aggregated configurable transceiver in an integrated circuit 有权
标题翻译：集成电路中的多协议通道聚合可配置收发器
公开(公告)号：US08165191B2
公开(公告)日：2012-04-24
申请号：US12288178
申请日：2008-10-17
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04B1/005 , G06F13/385 , H04L69/12 , H04L69/18
摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
摘要翻译：本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路从属（“PMD”）子层电路。

7. 发明授权

US08462908B2 Digital phase locked loop circuitry and methods 有权
标题翻译：数字锁相环电路及方法
公开(公告)号：US08462908B2
公开(公告)日：2013-06-11
申请号：US12974949
申请日：2010-12-21
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H03D3/24
CPC分类号： H03M9/00 , H03L7/089 , H03L2207/50 , H04L7/0008 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。出于同样的原因，发射侧可能会使用过量传输或过采样。

8. 发明申请

US20110211621A1 HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的宽范围可编程性的异构收发器架构
公开(公告)号：US20110211621A1
公开(公告)日：2011-09-01
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

9. 发明授权

US07397270B1 Dynamically-adjustable differential output drivers 有权
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07397270B1
公开(公告)日：2008-07-08
申请号：US11138919
申请日：2005-05-25
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

10. 发明授权

US07310399B1 Clock signal circuitry for multi-protocol high-speed serial interface circuitry 有权
公开(公告)号：US07310399B1
公开(公告)日：2007-12-18
申请号：US11650163
申请日：2007-01-05
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H04L25/40
CPC分类号： G06F1/10
摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

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