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1. 发明授权

CN102637996B 对称直接耦合激光器驱动器有权
公开(公告)号：CN102637996B
公开(公告)日：2017-03-01
申请号：CN201210026163.8
申请日：2012-02-07
申请人：马克西姆综合产品公司
发明人： J.C.阮 , A.K.费尔马
IPC分类号： H01S5/042
CPC分类号： H01S5/042 , H01S5/0261 , H01S5/0427 , H03K19/01837
摘要：用于高频应用的对称直接耦合激光器驱动器。该激光器驱动器采用集成电路的形式并且使用最少的相对小（低值）的外部部件用于驱动通过传输线耦合到激光器驱动器的激光二极管。可以使用可选的放大器来固定在数据频谱的内部节点处的电压以改善电路性能。还可以使用对偏置输入的反馈来固定在内部节点的电压。可以包括可编程序性和脉冲串模式能力。

2. 发明公开

CN102637996A 对称直接耦合激光器驱动器有权
公开(公告)号：CN102637996A
公开(公告)日：2012-08-15
申请号：CN201210026163.8
申请日：2012-02-07
申请人：马克西姆综合产品公司
发明人： J.C.阮 , A.K.费尔马
IPC分类号： H01S5/042
CPC分类号： H01S5/042 , H01S5/0261 , H01S5/0427 , H03K19/01837
摘要：用于高频应用的对称直接耦合激光器驱动器。该激光器驱动器采用集成电路的形式并且使用最少的相对小（低值）的外部部件用于驱动通过传输线耦合到激光器驱动器的激光二极管。可以使用可选的放大器来固定在数据频谱的内部节点处的电压以改善电路性能。还可以使用对偏置输入的反馈来固定在内部节点的电压。可以包括可编程序性和脉冲串模式能力。

3. 发明公开

CN101383162A 信号输出电路、光学拾取器和光学设备无效
公开(公告)号：CN101383162A
公开(公告)日：2009-03-11
申请号：CN200810144978.X
申请日：2008-08-18
申请人：索尼株式会社
发明人：中村仁
IPC分类号： G11B7/005 , G11B7/085 , G11B7/09 , H04L25/02
CPC分类号： H03K19/01825 , H03K17/16 , H03K19/01837
摘要：这里公开了一种信号输出电路、光学拾取器和光学设备。所述信号输出电路用于输出信号到具有给定传输特性的传输线上，所述信号输出电路包括：驱动电路，其适于通过电流驱动输入信号；以及输出电阻器，其连接到所述输出电路的输出级，并且能够根据其电阻调整输出信号波形，其中所述驱动电路的驱动电流和所述输出电阻器的电阻是可变的。

4. 发明公开

EP1213838A1 Integrated circuit device 审中-公开
标题翻译： Integrierte Schaltunganordnung
公开(公告)号：EP1213838A1
公开(公告)日：2002-06-12
申请号：EP01309139.2
申请日：2001-10-29
申请人： Nokia Corporation
发明人： Atkinson, Christopher
IPC分类号： H03K19/018 , H04M1/725 , H03K19/173
CPC分类号： H04M1/725 , H03K19/017581 , H03K19/01806 , H03K19/01837
摘要： An integrated circuit device 1 such as a current sensor includes a circuit configuration 3 which is driven from supply rails (P1, P2) at a given operational voltage. An external data connection P7 is arranged to supply data to a controlling micro-controller 2 that operates at a running voltage different from the voltage for the device 1. An enable connection (6) couples an enabling signal from the micro-controller 2 at its running voltage to pin P8 on the device 1. In response, the circuit configuration 3 supplies data for the micro-controller 2, to the data pin P7. The integrated circuit device 1 includes control circuitry (R1, T1) responsive to the enabling signal applied to pin P8 to ensure that the data supplied at pin P7 is at a voltage compatible with the running voltage of the micro-controller 2. No pin to receive a rail voltage corresponding to the running voltage for the micro-controller 2 is needed for the integrated circuit device 1.
摘要翻译：诸如电流传感器的集成电路装置1包括在给定工作电压下从电源轨（P1，P2）驱动的电路配置3。外部数据连接P7被布置为向控制微控制器2提供数据，控制微控制器2以与器件1的电压不同的运行电压进行操作。使能连接（6）将来自微控制器2的使能信号运行电压到器件1上的引脚P8。作为响应，电路配置3将数据引脚P7提供给微控制器2的数据。集成电路装置1包括响应于施加到引脚P8的使能信号的控制电路（R1，T1），以确保在引脚P7处提供的数据处于与微控制器2的运行电压兼容的电压。对于集成电路装置1需要接收与微控制器2的运行电压相对应的轨电压。

5. 发明授权

EP1057263B1 HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS 有权
标题翻译：集成的电路架构用于快速引脚驱动器为市售的自动测试设备应用
公开(公告)号：EP1057263B1
公开(公告)日：2003-05-21
申请号：EP99967393.2
申请日：1999-12-16
申请人： TelASIC Communications, Inc.
发明人： LINDER, Lloyd, F.
IPC分类号： H03K19/003 , H03K17/66 , G01R31/319 , H03K19/018
CPC分类号： H03K19/01837 , G01R31/31924 , H03K19/00376 , H03K19/01806
摘要： An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

6. 发明公开

EP1057263A1 HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS 有权
标题翻译：集成的电路架构用于快速引脚驱动器为市售的自动测试设备应用
公开(公告)号：EP1057263A1
公开(公告)日：2000-12-06
申请号：EP99967393.2
申请日：1999-12-16
申请人： Raytheon Company
发明人： LINDER, Lloyd, F.
IPC分类号： H03K19/003 , H03K17/66 , G01R31/319 , H03K19/018
CPC分类号： H03K19/01837 , G01R31/31924 , H03K19/00376 , H03K19/01806
摘要： An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

7. 发明申请

WO00039928A1 HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS 审中-公开
标题翻译：用于商业自动测试设备应用的高速引脚集成电路架构
公开(公告)号：WO00039928A1
公开(公告)日：2000-07-06
申请号：PCT/US1999/030120
申请日：1999-12-16
IPC分类号： G01R31/28 , G01R31/319 , H03K19/003 , H03K19/013 , H03K19/018 , H03K17/66
CPC分类号： H03K19/01837 , G01R31/31924 , H03K19/00376 , H03K19/01806
摘要： An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.
摘要翻译：改进的高速PIN驱动器集成电路和架构。 PIN驱动电路的结构在有源模式下不依赖于正常工作时的晶体管钳位，并且在抑制模式或主动模式下不需要高反向基极 - 发射极击穿电压，这与高速时的高速性能直接相反针对CMOS，TTL，ECL电平兼容性的PIN电压偏移。特别地，PIN驱动器电路始终是有源线性电路，并且始终保护任何晶体管的反向基极 - 发射极电压，并且不需要线或或钳位晶体管。该架构使用复制偏移来在禁止模式下取消PIN驱动器的电流，这是在禁止模式下在PIN处产生的漏电流的自动测试设备的要求未被校准的。使用电流镜像电路，求和装置和缓冲电路来实现复制偏置，该电路在PIN驱动器电路的活动模式下产生电压副本。本发明中使用的复制偏移方案跟踪温度和过程，并提供改进的高速电路，而不需要在禁止模式下校准泄漏电流。

8. 发明授权

US06586967B2 Integrated circuit device having data signal output at voltage level of the device coupled thereto 有权
标题翻译：具有在与其耦合的装置的电压电平处输出的数据信号的集成电路装置
公开(公告)号：US06586967B2
公开(公告)日：2003-07-01
申请号：US09996067
申请日：2001-11-28
申请人： Christopher Atkinson
发明人： Christopher Atkinson
IPC分类号： H03K190175
CPC分类号： H04M1/725 , H03K19/017581 , H03K19/01806 , H03K19/01837
摘要： An integrated circuit device 1 such as a current sensor includes a circuit configuration 3 which is driven from supply rails (P1, P2) at a given operational voltage. The integrated circuit device 1 includes control circuitry (R1, T1) responsive to an enabling signal from a micro-controller 2 applied to pin P8 to ensure that data supplied at pin P7 to the micro-controller is at a voltage compatible with a running voltage of the micro-controller 2 that is different from that of the device 1. No pin to receive a rail voltage corresponding to the running voltage for the micro-controller 2 is needed for the integrated circuit device 1.
摘要翻译：诸如电流传感器的集成电路装置1包括在给定工作电压下从电源轨（P1，P2）驱动的电路配置3。集成电路装置1包括响应于施加到引脚P8的微控制器2的使能信号的控制电路（R1，T1），以确保在引脚P7处向微控制器提供的数据处于与运行电压兼容的电压对于集成电路装置1，不需要与微控制器2的运行电压对应的导轨电压的引脚。

9. 发明授权

US06362644B1 Programmable termination for integrated circuits 有权
标题翻译：集成电路的可编程终端
公开(公告)号：US06362644B1
公开(公告)日：2002-03-26
申请号：US09630090
申请日：2000-08-01
申请人： Philip A. Jeffery , Stephen G. Shook
发明人： Philip A. Jeffery , Stephen G. Shook
IPC分类号： H03K1716
CPC分类号： H03K19/01837
摘要： A receiver circuit (16) is programmable to operate with different logic family driver circuits (10). The receiver circuit has two external configuration pins (22,) 24) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit (16) for an ECL application will require first and second configuration pins (22,24) are connected to VCC—2 volts. To terminate the receiver circuit (16) for a CML application will require the first configuration pin (22) and the second configuration pin (24) are connected to VCC. LVDS termination for the receiver circuit (16) requires the first configuration pin (22) and the second configuration pin (24) are connected together. The configuration pins are external to a semiconductor package (14) housing the receiver circuit.
摘要翻译：接收器电路（16）可编程为与不同的逻辑系列驱动电路（10）一起工作。接收器电路具有两个外部配置引脚（22），其被配置为为所使用的逻辑系列驱动器电路的类型提供必要的端接。为了终止用于ECL应用的接收机电路（16），将需要将第一和第二配置引脚（22,24）连接到VCC-2伏特。为了终止用于CML应用的接收机电路（16）将需要第一配置引脚（22）和第二配置引脚（24）连接到VCC。接收器电路（16）的LVDS终端需要第一配置引脚（22）和第二配置引脚（24）连接在一起。配置引脚位于容纳接收器电路的半导体封装（14）的外部。

10. 发明授权

US06300802B1 Output buffer with programmable voltage swing 有权
标题翻译：具有可编程电压摆幅的输出缓冲器
公开(公告)号：US06300802B1
公开(公告)日：2001-10-09
申请号：US09253621
申请日：1999-02-19
申请人： Kenneth Smetana
发明人： Kenneth Smetana
IPC分类号： H03K19086
CPC分类号： H03K19/01837
摘要： An integrated circuit device in which the magnitude of the output voltage swings of outputs in a circuit having emitter coupled output transistors is programmable includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the base of a current source transistor in order to program the magnitude of the output voltage swings. An electrical connection area of the integrated circuit device is connected to the bias voltage generator. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired magnitude of the output voltage swings. The external programming circuit typically can be a resistance or an external voltage source. The variable bias generator can be any of a number of circuits that produce a bias voltage that is dependent upon the external programming circuit connected to the electrical connection area, and that produce a default bias voltage if no external programming circuit is connected to the electrical connection area. Another aspect of the invention is a method for programming the magnitude of the output voltage swings in an integrated circuit device having emitter coupled output transistors. The invention provides the ability to program the magnitude of the output voltage swings of the outputs to increase the magnitude of the output voltage swings, or alternatively, to decrease the magnitude of the output voltage swings thereby advantageously saving power and preventing unnecessary heat generation.
摘要翻译：一种集成电路装置，其中具有发射极耦合输出晶体管的电路中的输出的输出电压摆幅的大小可编程包括产生偏置电压的可变偏置发生器。偏置电压连接到电流源晶体管的基极，以便对输出电压摆幅的幅度进行编程。集成电路装置的电连接区域连接到偏置电压发生器。外部编程电路可以连接到电连接区域以便设置偏置电压，从而编程输出电压摆幅的期望幅度。外部编程电路通常可以是电阻或外部电压源。可变偏置发生器可以是产生取决于连接到电连接区域的外部编程电路的偏置电压的多个电路中的任何一个，并且如果没有外部编程电路连接到电连接，则产生默认偏置电压区。本发明的另一方面是一种用于对具有发射极耦合输出晶体管的集成电路器件中的输出电压摆幅的幅度进行编程的方法。本发明提供了对输出的输出电压摆幅的幅度进行编程以增加输出电压摆幅的幅度的能力，或者替代地，减小输出电压摆幅的大小，从而有利地节省功率并防止不必要的发热。

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