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1. 发明授权

US5113511A System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions 失效
标题翻译：基于指令动态提供预处理高速/慢速存取存储器到处理单元的系统
公开(公告)号：US5113511A
公开(公告)日：1992-05-12
申请号：US360357
申请日：1989-06-02
申请人： Craig Nelson , Javier Solis , David L. Needle
发明人： Craig Nelson , Javier Solis , David L. Needle
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： A system (60) for predicting CPU addresses includes a CPU (34) connected by bus (62) to page mode address predicting circuit (64). The page mode address predicting circuit (64) is connected to memory arbitration circuits (66) by bus (68). The memory arbitration circuits (66) are connected to RAM (42) by address, data and control busses (44), (46) and (48). The CPU (34), page mode address predicting circuit (64) and the memory arbitration circuits 66 are contained in a microprocessor integrated circuit (32). The page mode predicting circuit 64 examines signals from the CPU (34) to be supplied to the data bus (46) at the time of a SYNC pulse. This operation results in examination of the first byte of a CPU instruction to determine how many of the following memory accesses will be able to be carried out in high speed mode. If it is determined that the next memory access will be able to be carried out in the high speed mode, then the next memory cycle is performed using a high speed access mode of the RAM (42), e.g. page mode access.
摘要翻译：用于预测CPU地址的系统（60）包括通过总线（62）连接到页模式地址预测电路（64）的CPU（34）。页模式地址预测电路（64）通过总线（68）连接到存储器仲裁电路（66）。存储器仲裁电路（66）通过地址，数据和控制总线（44），（46）和（48）连接到RAM（42）。 CPU（34），页模式地址预测电路（64）和存储器仲裁电路66被包含在微处理器集成电路（32）中。页模式预测电路64在SYNC脉冲时检查来自CPU（34）的信号以提供给数据总线（46）。该操作导致检查CPU指令的第一个字节，以确定能够在高速模式下执行多少个以下存储器访问。如果确定下一个存储器访问将能够在高速模式下执行，则使用RAM（42）的高速存取模式来执行下一个存储周期，例如，页面模式访问。

2. 发明授权

US5260941A Digital radio telephone system 失效
标题翻译：数字无线电话系统
公开(公告)号：US5260941A
公开(公告)日：1993-11-09
申请号：US890720
申请日：1992-05-29
申请人： Ronald Wilder , Gregory Pierce , Richard C. Frey , Whitney E. Childs-Goodrich , David L. Needle
发明人： Ronald Wilder , Gregory Pierce , Richard C. Frey , Whitney E. Childs-Goodrich , David L. Needle
IPC分类号： H04W84/16 , H04L5/22
CPC分类号： H04W84/16
摘要： The telephone system of the present invention is realized by a unique dynamic time slice architecture which allows for up to 480 transfers of data. A dual port RAM is utilized in which are stored two pages of data, containing time slice information identifying the sending and receiving devices for each time slice slot within the frame. The time slice configuration can be easily modified to accommodate a change in the current system configuration, for example, a handset connecting or disconnecting from a central office line, or the initiation of a conference call. The time slice configuration is modified by updating the second page and swapping the two pages at the beginning of the next frame so that the time slice controller accesses the second page and the configurations specified therein. Thus the system can be updated and controlled in real time with no delays to the users of the telephone system. The telephone system of the present invention further provides a dynamic conferencing capability which can accommodate a large number of users with no additional circuitry and little additional system overhead. The conferencing circuit linearly combines digitized audio data received from different sources over successive time slice slots in a single frame on a real time basis wherein parties can be added or removed simply by adding or removing the connections to the time slice slots.
摘要翻译：本发明的电话系统通过独特的动态时间片结构来实现，其允许多达480个数据传输。使用双端口RAM，其中存储两页数据，其中包含标识帧内每个时间片时隙的发送和接收设备的时间片信息。可以容易地修改时间片配置以适应当前系统配置的变化，例如，连接或断开与中心局线路的手机或者召开电话会议。通过更新第二页并在下一帧的开头交换两个页面来修改时间片配置，使得时间片控制器访问第二页以及其中指定的配置。因此，可以实时更新和控制系统，而不会延迟电话系统的用户。本发明的电话系统还提供动态会议能力，其可以容纳大量用户，没有额外的电路和少量额外的系统开销。会议电路在实时基础上将单个帧中连续时间片时隙上的从不同来源接收的数字化音频数据线性组合，其中可以通过添加或去除与时间片时隙的连接来简单地添加或删除各方。

3. 发明授权

US5128928A Digital radio telephone system 失效
标题翻译：数字无线电电话系统
公开(公告)号：US5128928A
公开(公告)日：1992-07-07
申请号：US609000
申请日：1990-10-31
申请人： Ronald P. Wilder , Gregory Pierce , Richard C. Frey , Whitney E. Childs-Goodrich , David L. Needle
发明人： Ronald P. Wilder , Gregory Pierce , Richard C. Frey , Whitney E. Childs-Goodrich , David L. Needle
IPC分类号： H04M3/56 , H04W84/16
CPC分类号： H04W84/16
摘要： The telephone system of the present invention is realized by a unique dynamic time slice architecture which allows for up to 480 transfers of data. A dual port RAM is utilized in which are stored two pages of data, containing time slice information identifying the sending and receiving devices for each time slice slot within the frame. The time slice configuration can be easily modified to accommodate a change in the current system configuration, for example, a handset connecting or disconnecting from a central office line, or the initiation of a conference call. The time slice configuration is modified by updating the second page and swapping the two pages at the beginning of the next frame so that the time slice controller accesses the second page and the configurations specified therein. Thus the system can be updated and controlled in real time with no delays to the users of the telephone system. The telephone system of the present invention further provides a dynamic conferencing capability which can accommodate a large number of users with no additional circuitry and little additional system overhead. The conferencing circuit linearly combines digitized audio data received from different sources over successive time slice slots in a single frame on a real time basis wherein parties can be added or removed simply by adding or removing the connections to the time slice slots.
摘要翻译：本发明的电话系统通过独特的动态时间片结构来实现，其允许多达480个数据传输。使用双端口RAM，其中存储两页数据，其中包含标识帧内每个时间片时隙的发送和接收设备的时间片信息。可以容易地修改时间片配置以适应当前系统配置的变化，例如，连接或断开与中心局线路的手机或者召开电话会议。通过更新第二页并在下一帧的开头交换两个页面来修改时间片配置，使得时间片控制器访问第二页以及其中指定的配置。因此，可以实时更新和控制系统，而不会延迟电话系统的用户。本发明的电话系统还提供动态会议能力，其可以容纳大量用户，没有额外的电路和少量额外的系统开销。会议电路在实时基础上将单个帧中连续时间片时隙上的从不同来源接收的数字化音频数据线性组合，其中可以通过添加或去除与时间片时隙的连接来简单地添加或删除各方。

4. 发明授权

US5752073A Digital signal processor architecture 失效
标题翻译：数字信号处理器架构
公开(公告)号：US5752073A
公开(公告)日：1998-05-12
申请号：US501163
申请日：1995-07-11
申请人： Donald M. Gray, III , David L. Needle
发明人： Donald M. Gray, III , David L. Needle
IPC分类号： G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3001 , G06F9/30094 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3867
摘要： A digital signal processing architecture is inherently cyclical in nature, by providing a timer which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input sample stream. Pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers. The processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO. Similarly, whenever the processor writes data to one of the locations corresponding to an output FIFO, control means automatically recognizes that and copies the data into the corresponding output FIFO. Output FIFO writes may be emulated by an address latch and a data latch in a path to the FIFOs. The processor also includes instructions with a "write-back" bit, a novel register addressing mode, a "branch from" instruction, an invisible move function, and an operand mask register.
摘要翻译：数字信号处理架构本质上是周期性的，通过提供定时器，其可以被编程以重置处理器并且周期性地返回到第一指令，通常一次输入样本流的每个采样。通过使用双缓冲系统来增强管道操作，其中操作数一旦被准备就被锁存在双缓冲器的第一级中，但是只有当最后一个就绪操作数可用时它们被传送到第二级，计算单元准备好接收操作数。计算单元接收缓冲器的第二级中的操作数。处理器通过随机存取存储器和多个FIFO与外部单元进行通信。每个FIFO与随机存取存储器中的相应位置相关联。每当处理器从随机存取存储器中的这些位置中的一个获取值时，控制装置自动将该位置从相应的FIFO重新填充。类似地，只要处理器将数据写入对应于输出FIFO的位置之一，控制装置自动识别并将数据复制到相应的输出FIFO中。输出FIFO写操作可以通过FIFO中的地址锁存器和数据锁存器进行仿真。该处理器还包括具有“回写”位，新型寄存器寻址模式，“分支从”指令，不可见移动功能和操作数掩码寄存器的指令。

5. 发明授权

US5091941A Secure voice data transmission system 失效
标题翻译：安全语音数据传输系统
公开(公告)号：US5091941A
公开(公告)日：1992-02-25
申请号：US607988
申请日：1990-10-31
申请人： David L. Needle , Bradley C. Stribling
发明人： David L. Needle , Bradley C. Stribling
IPC分类号： H04L9/06 , H04K1/00 , H04L9/14 , H04L9/18 , H04M1/00
CPC分类号： H04K1/006
摘要： In the secure radio transmission system of the present invention the sign bit for each byte of audio digital data is scrambled to generate a scrambled sign bit. By altering the sign bit, the resultant sound is significantly affected regardless of the amplitude range of the source audio. A key is stored in each authorized radio transmitter/receiver telephone. The key is used to select the bits of the digital voice data to be transmitted which are used to scramble the sign bit. The selected bits of the voice data are then used to scramble the sign bit and the voice data with the scrambled sign bit are transmitted to the receiving device. The receiving device executes the reverse process wherein the receiving device selects predetermined bits of the received voice data according to the key stored in the receiving device and scrambles the scrambled sign bit using the same algorithm in accordance with the data bits selected. This process generates the unscrambled sign bit and unscrambled voice data is generated at the output of the receiving device.
摘要翻译：在本发明的安全无线电传输系统中，音频数字数据的每个字节的符号位被加扰以产生加扰符号位。通过改变符号位，无论源音频的幅度范围如何，所得到的声音都会受到很大的影响。密钥存储在每个授权的无线电发射机/接收机电话中。该密钥用于选择用于加扰符号位的要发送的数字语音数据的位。然后使用语音数据的所选位来加扰符号位，并将具有加扰符号位的语音数据发送到接收设备。接收装置执行相反处理，其中接收装置根据存储在接收装置中的密钥来选择接收到的语音数据的预定比特，并根据所选择的数据比特使用相同的算法对加扰符号比特进行加扰。该过程产生未加扰的符号位，并且在接收设备的输出处产生未加扰的语音数据。

6. 发明授权

US4988892A Method and circuit for generating dependent clock signals 失效
标题翻译：用于产生相关时钟信号的方法和电路
公开(公告)号：US4988892A
公开(公告)日：1991-01-29
申请号：US361020
申请日：1989-06-02
申请人： David L. Needle
发明人： David L. Needle
IPC分类号： G06F1/04 , G06F1/10 , H03K5/00 , H03K5/156
CPC分类号： G06F1/04 , G06F1/10 , H03K5/00006 , H03K5/156
摘要： A method and circuit generate a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal and inverting it to create a second master clock signal that is one hundred eighty degrees out of phase with the first master clock signal. The second master clock signal is used to drive a flip flop type circuit so that the flip flop circuit changes states when the first master clock signal is at a "zero" level and the second master clock signal is at a "one " level. The output of the flip flop circuit is enabled using the first master clock signal. Connected to the output of the tri-state driver is a repeater circuit of the type having an output that remains the same as the input until the input level is changed. The resulting dependent clock signal has a minimal skew with respect to the first master clock signal because the output of the flip flop circuit has become stable by the time the tri-state driver is enabled by the first master clock signal. Thus, the skew line is limited to the delay time of the tri-state driver.
摘要翻译：一种方法和电路从主时钟信号产生从属时钟信号，相对于主时钟信号具有相关时钟信号的最小偏移并将其反相以产生与第一主时钟信号相差十八十度的第二主时钟信号，第一主时钟信号。第二主时钟信号用于驱动触发器型电路，使得当第一主时钟信号处于“零”电平并且第二主时钟信号处于“一”电平时触发电路改变状态。使用第一主时钟信号使能触发电路的输出。连接到三态驱动器的输出的是具有与输入保持相同的输出的类型的中继器电路，直到输入电平改变为止。所产生的从属时钟信号相对于第一主时钟信号具有最小的偏移，因为触发电路的输出在三态驱动器被第一主时钟信号使能时变得稳定。因此，偏斜线限于三态驱动器的延迟时间。

7. 发明授权

US06191772B1 Resolution enhancement for video display using multi-line interpolation 失效
标题翻译：使用多行插值的视频显示分辨率增强
公开(公告)号：US06191772B1
公开(公告)日：2001-02-20
申请号：US09110117
申请日：1998-07-02
申请人： Robert J. Mical , David L. Needle , Teju J. Khubchandani , Stephen H. Landrum
发明人： Robert J. Mical , David L. Needle , Teju J. Khubchandani , Stephen H. Landrum
IPC分类号： G09G106
CPC分类号： G06T3/4007 , G06F17/175 , G09G5/06 , G09G5/39 , G09G5/391 , G09G5/395 , G09G2360/121
摘要： The invention provides a method and apparatus for enhancing apparent image resolution by way of multi-line interpolation. A method for enhancing the resolution of low-resolution image-data includes the steps of: providing a memory [420] having independently addressable storage banks [420L,420R]; storing the low-resolution image-data [125] in the memory [420] such that low-resolution image-data defining a first low-resolution row [LR0] resides in a first of said storage banks [420R] and such that low-resolution image-data defining a second low-resolution row [LR1], adjacent to the first low-resolution row [LR0], resides in a second of said storage banks [420L]; extracting first through Nth low-resolution pixel signals [S1-S1] from the memory [420], said signals representing values of low-resolution pixels in the adjacent first and second low-resolution rows [LR0,LR1] of the low-resolution image-data [125]; and producing a high-resolution pixel signal [Hpx] from said first through Nth low-resolution pixel signals [S1-S3] in accordance with a distance-weighted algorithm.
摘要翻译：本发明提供一种通过多线插值增强视觉图像分辨率的方法和装置。一种用于增强低分辨率图像数据的分辨率的方法包括以下步骤：提供具有独立可寻址存储体[420L，420R]的存储器[420]。将低分辨率图像数据[125]存储在存储器420中，使得限定第一低分辨率行[LR0]的低分辨率图像数据驻留在所述存储库[420R]中的第一个中，并且使得低定义与第一低分辨率行[LR0]相邻的第二低分辨率行[LR1]的分辨率图像数据驻留在所述存储库[420L]中的第二个中。从存储器[420]提取第一至第N低分辨率像素信号[S1-S1]，所述信号表示低分辨率的相邻第一和第二低分辨率行[LR0，LR1]中的低分辨率像素的值图像数据[125]; 并根据距离加权算法从所述第一至第N低分辨率像素信号[S1-S3]产生高分辨率像素信号[Hpx]。

8. 发明授权

US5838389A Apparatus and method for updating a CLUT during horizontal blanking 失效
标题翻译：在水平消隐期间更新CLUT的装置和方法
公开(公告)号：US5838389A
公开(公告)日：1998-11-17
申请号：US300867
申请日：1994-09-02
申请人： Robert J. Mical , David L. Needle , Teju J. Khubchandani
发明人： Robert J. Mical , David L. Needle , Teju J. Khubchandani
IPC分类号： G09G5/06 , G09G5/18 , G09G5/39 , G09G5/395 , H04N9/64
CPC分类号： G09G5/18 , G09G5/06
摘要： An apparatus and method for updating a color look up table and expanding video data for use in various applications such as a multimedia computer. The color look up table updating scheme permits selective updating of one entry in the table or up to all of the entries in the table. Updating of the color look up table is preferably performed during the horizontal blanking period. The table may be comprised of two buffers, and a combined output of these two buffers further enhances a multiplicity of colors available to a user.
摘要翻译：一种用于更新彩色查找表并扩展用于诸如多媒体计算机的各种应用中的视频数据的装置和方法。颜色查找表更新方案允许选择性地更新表中的一个条目或直到表中的所有条目。优选在水平消隐期间执行颜色查找表的更新。该表可以由两个缓冲器组成，并且这两个缓冲器的组合输出进一步增强了用户可用的多种颜色。

9. 发明授权

US5502462A Display list management mechanism for real-time control of by-the-line modifiable video display system 失效
标题翻译：显示列表管理机制，用于实时控制线上可修改的视频显示系统
公开(公告)号：US5502462A
公开(公告)日：1996-03-26
申请号：US146505
申请日：1993-11-01
申请人： Robert J. Mical , David L. Needle , Stephen H. Landrum , Teju Khubchandani
发明人： Robert J. Mical , David L. Needle , Stephen H. Landrum , Teju Khubchandani
IPC分类号： G06T15/70 , G09G5/02 , G09G5/06 , G09G5/00
CPC分类号： G09G5/06 , G09G5/02
摘要： The invention provides a method and apparatus for managing color modification of a raster based image on a real time, line-by-line basis and for managing real-time of new imagery into buffers whose data is displayable.
摘要翻译：本发明提供了一种用于基于逐行的基准实时管理基于光栅的图像的颜色修改的方法和装置，并且用于将新的图像实时管理到数据可显示的缓冲器中。

10. 发明授权

US5481275A Resolution enhancement for video display using multi-line interpolation 失效
标题翻译：使用多行插值的视频显示分辨率增强
公开(公告)号：US5481275A
公开(公告)日：1996-01-02
申请号：US970287
申请日：1992-11-02
申请人： Robert J. Mical , David L. Needle , Teju J. Khubchandani , Stephen H. Landrum
发明人： Robert J. Mical , David L. Needle , Teju J. Khubchandani , Stephen H. Landrum
IPC分类号： G06F17/17 , G06T3/40 , G09G5/06 , G09G5/39 , G09G5/391 , G09G5/395 , G09G1/06
CPC分类号： G06T3/4007 , G06F17/175 , G09G5/06 , G09G5/39 , G09G5/391 , G09G2360/121 , G09G5/395
摘要： The invention provides a method and apparatus for enhancing apparent image resolution by way of multi-line interpolation. A method for enhancing the resolution of low-resolution image-data includes the steps of: providing a memory having independently addressable storage banks; storing the low-resolution image-data in the memory such that low-resolution image-data defining a first low-resolution row resides in a first of said storage banks and such that low-resolution image-data defining a second low-resolution row, adjacent to the first low-resolution row, resides in a second of said storage banks; extracting first through Nth low-resolution pixel signals from the memory, said signals representing values of low-resolution pixels in the adjacent first and second low-resolution rows of the low-resolution image-data; and producing a high-resolution pixel signal from said first through Nth low-resolution pixel signals in accordance with a distance-weighted algorithm.
摘要翻译：本发明提供一种通过多线插值增强视觉图像分辨率的方法和装置。一种用于增强低分辨率图像数据的分辨率的方法包括以下步骤：提供具有独立可寻址存储体的存储器; 将低分辨率图像数据存储在存储器中，使得限定第一低分辨率行的低分辨率图像数据驻留在所述存储库中的第一个存储体中，并且使得限定第二低分辨率行的低分辨率图像数据与第一低分辨率行相邻，位于所述存储库中的第二个中; 从存储器提取第一至第N低分辨率像素信号，所述信号表示低分辨率图像数据的相邻第一和第二低分辨率行中的低分辨率像素的值; 以及根据距离加权算法从所述第一至第N低分辨率像素信号产生高分辨率像素信号。

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