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1. 发明申请

US20070020394A1 Methods and apparatus for vapor processing of micro-device workpieces 审中-公开
标题翻译：微器件工件蒸汽加工的方法和装置
公开(公告)号：US20070020394A1
公开(公告)日：2007-01-25
申请号：US11540850
申请日：2006-09-28
申请人： Craig Carpenter , Ross Dando , Dan Gealy , Garo Derderian , Allen Mardian
发明人： Craig Carpenter , Ross Dando , Dan Gealy , Garo Derderian , Allen Mardian
IPC分类号： C23C16/00 , B05D1/04
CPC分类号： C23C16/4481
摘要： CVD, ALD, and other vapor processes used in processing semiconductor workpieces often require volatilizing a liquid or solid precursor. Certain embodiments of the invention provide improved and/or more consistent volatilization rates by moving a reaction vessel. In one exemplary embodiment, a reaction vessel is rotated about a rotation axis which is disposed at an angle with respect to vertical. This deposits a quantity of the reaction precursor on an interior surface of the vessel's sidewall which is exposed to the headspace as the vessel rotates. Other embodiments employ drivers adapted to move the reaction vessel in other manners, such as a pendulum arm to oscillate the vessel along an arcuate path or a mechanical linkage which moves the vessel along an elliptical path.
摘要翻译：用于处理半导体工件中的CVD，ALD和其它蒸气方法通常需要挥发液体或固体前体。本发明的某些实施方案通过移动反应容器提供改进的和/或更一致的挥发速率。在一个示例性实施例中，反应容器围绕相对于垂直方向以一定角度设置的旋转轴线旋转。这将一定数量的反应前体沉积在容器侧壁的内表面上，该容器的侧壁在容器旋转时暴露于顶部空间。其他实施例使用适于以其他方式移动反应容器的驱动器，例如摆臂，以沿着沿着椭圆形路径移动容器的弓形路径或机械连杆摆动容器。

2. 发明申请

US20050133161A1 Apparatus and method for depositing materials onto microelectronic workpieces 失效
标题翻译：将材料沉积到微电子工件上的装置和方法
公开(公告)号：US20050133161A1
公开(公告)日：2005-06-23
申请号：US10933604
申请日：2004-09-02
申请人： Craig Carpenter , Allen Mardian , Ross Dando , Kimberly Tschepen , Garo Derderian
发明人： Craig Carpenter , Allen Mardian , Ross Dando , Kimberly Tschepen , Garo Derderian
IPC分类号： C23C16/44 , C23C16/455 , C23F1/00
CPC分类号： C23C16/45544 , C23C16/45565
摘要： Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto microelectronic workpieces. In one embodiment, a reactor for vapor deposition of a material comprises a reaction chamber and a gas distributor. The reaction chamber can include an inlet and an outlet. The gas distributor is positioned in the reaction chamber. The gas distributor has a compartment coupled to the inlet to receive a gas flow and a distributor plate including a first surface facing the compartment, a second surface facing the reaction chamber, and a plurality of passageways. The passageways extend through the distributor plate from the first surface to the second surface. Additionally, at least one of the passageways has at least a partially occluded flow path through the plate. For example, the occluded passageway can be canted at an oblique angle relative to the first surface of the distributor plate so that gas flowing through the canted passageway changes direction as it passes through the distributor plate.
摘要翻译：用于将材料气相沉积到微电子工件上的反应器，包括这种反应器的系统以及将材料沉积到微电子工件上的方法。在一个实施方案中，用于气相沉积材料的反应器包括反应室和气体分配器。反应室可以包括入口和出口。气体分配器位于反应室中。气体分配器具有联接到入口以接收气流的隔室和分布板，分配器板包括面向隔室的第一表面，面对反应室的第二表面和多个通道。通道从第一表面延伸穿过分配器板到第二表面。此外，至少一个通道具有穿过板的至少一部分闭塞的流动路径。例如，封闭通道可以相对于分配器板的第一表面倾斜地倾斜，使得流过倾斜通道的气体在通过分配器板时改变方向。

3. 发明申请

US20050022739A1 Apparatus and method for depositing materials onto microelectronic workpieces 审中-公开
公开(公告)号：US20050022739A1
公开(公告)日：2005-02-03
申请号：US10933605
申请日：2004-09-02
申请人： Craig Carpenter , Allen Mardian , Ross Dando , Kimberly Tschepen , Garo Derderian
发明人： Craig Carpenter , Allen Mardian , Ross Dando , Kimberly Tschepen , Garo Derderian
IPC分类号： C23C16/44 , C23C16/455 , C23C16/00
CPC分类号： C23C16/45544 , C23C16/45565
摘要： Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto microelectronic workpieces. In one embodiment, a reactor for vapor deposition of a material comprises a reaction chamber and a gas distributor. The reaction chamber can include an inlet and an outlet. The gas distributor is positioned in the reaction chamber. The gas distributor has a compartment coupled to the inlet to receive a gas flow and a distributor plate including a first surface facing the compartment, a second surface facing the reaction chamber, and a plurality of passageways. The passageways extend through the distributor plate from the first surface to the second surface. Additionally, at least one of the passageways has at least a partially occluded flow path through the plate. For example, the occluded passageway can be canted at an oblique angle relative to the first surface of the distributor plate so that gas flowing through the canted passageway changes direction as it passes through the distributor plate.

4. 发明申请

US20060249253A1 Manifold assembly for feeding reactive precursors to substrate processing chambers 审中-公开
公开(公告)号：US20060249253A1
公开(公告)日：2006-11-09
申请号：US11481460
申请日：2006-07-05
申请人： Ross Dando , Craig Carpenter , Garo Derderian
发明人： Ross Dando , Craig Carpenter , Garo Derderian
IPC分类号： H01L21/306
CPC分类号： C23C16/4408 , C23C16/455 , C23C16/45561
摘要： A reactive precursor feeding manifold assembly includes a body comprising a plenum chamber. A valve is received proximate the body and has at least two inlets and at least one outlet. At least one valve inlet is configured for connection with a reactive precursor source. At least one valve outlet feeds to a precursor inlet to the plenum chamber. A purge stream is included which has a purge inlet to the plenum chamber which is received upstream of the plenum chamber precursor inlet. The body has a plenum chamber outlet configured to connect with a substrate processing chamber. In one implementation, the plenum chamber purge inlet is angled from the plenum chamber precursor inlet. In one implementation, structure is included on the body which is configured to mount the body to a substrate processing chamber with the plenum chamber outlet proximate to and connected with a substrate processing chamber inlet.

5. 发明申请

US20060065635A1 Deposition chamber surface enhancement and resulting deposition chambers 审中-公开
标题翻译：沉积室表面增强和沉积室
公开(公告)号：US20060065635A1
公开(公告)日：2006-03-30
申请号：US11271673
申请日：2005-11-09
申请人： Garo Derderian , Gurtej Sandhu , Ross Dando , Craig Carpenter , Philip Campbell
发明人： Garo Derderian , Gurtej Sandhu , Ross Dando , Craig Carpenter , Philip Campbell
IPC分类号： C23C16/52 , C03C15/00
CPC分类号： H01J37/32477 , C23C16/4404 , H01J37/3244 , H01J2237/022
摘要： Methods for passivating exposed surfaces within an apparatus for depositing thin films on a substrate are disclosed. Interior surfaces of a deposition chamber and conduits in communication therewith are passivated to prevent reactants used in a deposition process and reaction products from adsorbing or chemisorbing to the interior surfaces. The surfaces may be passivated for this purpose by surface treatments, lining, temperature regulation, or combinations thereof. A method for determining a temperature or temperature range at which to maintain a surface to minimize accumulation of reactants and reaction products is also disclosed. A deposition apparatus with passivated surfaces within the deposition chamber and gas flow paths is also disclosed.
摘要翻译：公开了在用于在衬底上沉积薄膜的装置中的暴露表面钝化的方法。沉积室的内表面和与其连通的导管被钝化以防止在沉积过程中使用的反应物和反应产物吸附或化学吸附到内表面。表面可以通过表面处理，衬里，温度调节或其组合来钝化。还公开了用于确定维持表面以使反应物和反应产物的积聚最小化的温度或温度范围的方法。还公开了在沉积室和气体流动路径内具有钝化表面的沉积设备。

6. 发明授权

US07390710B2 Protection of tunnel dielectric using epitaxial silicon 有权
标题翻译：使用外延硅保护隧道电介质
公开(公告)号：US07390710B2
公开(公告)日：2008-06-24
申请号：US10932795
申请日：2004-09-02
申请人： Garo Derderian , Nirmal Ramaswamy
发明人： Garo Derderian , Nirmal Ramaswamy
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336
摘要： Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.
摘要翻译：使用外延硅层来保护浮栅存储器单元的隧道介电层免于在形成浅沟槽隔离（STI）区域期间的过度氧化或去除。在沟槽形成之后，外延硅层从隧道介电层的相对侧上的含硅层生长，从而允许其厚度被限制为隧道介电层的厚度的大约二分之一。外延硅可以在用电介质材料填充沟槽之前被氧化，或者在氧化至少覆盖隧道介电层的端部的外延硅之前可能发生电介质填充。

7. 发明申请

US20070148932A9 Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition 失效
标题翻译：使用原子层沉积形成铌和/或含钒层的系统和方法
公开(公告)号：US20070148932A9
公开(公告)日：2007-06-28
申请号：US10923315
申请日：2004-08-20
申请人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
发明人： Garo Derderian , Donald Westmoreland , Stefan Uhlenbrook
IPC分类号： H01L21/20
CPC分类号： H01L21/02205 , C23C16/405 , C23C16/45553 , H01L21/02175 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31604 , H01L28/90
摘要： A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
摘要翻译：使用一种或多种包括铌和/或钒的前体化合物在基板上，特别是用于制造半导体或存储器件结构的半导体衬底或衬底组件中形成（以及用于形成）含金属层的方法以及使用包括多个沉积循环的原子层沉积工艺。

8. 发明申请

US20070141835A1 Methods of fabricating interconnects for semiconductor components 有权
标题翻译：制造半导体元件互连的方法
公开(公告)号：US20070141835A1
公开(公告)日：2007-06-21
申请号：US11705897
申请日：2007-02-13
申请人： Kyle Kirby , Shuang Meng , Garo Derderian
发明人： Kyle Kirby , Shuang Meng , Garo Derderian
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： C23C16/34 , C23C16/45525 , C23C18/1608 , C23C18/1879 , C23C18/36 , H01L21/28562 , H01L21/288 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
摘要翻译：一方面，本发明包括制造用于半导体部件的互连的方法。提供半导体衬底，并且形成完全贯穿衬底的开口。第一种材料在小于或等于约200℃的温度下沿着开口的侧壁沉积。沉积可以包括原子层沉积和化学气相沉积中的一个或两个，并且第一材料可以包括金属氮化物。在第一材料的表面上形成焊料润湿材料。焊料润湿材料可以包括例如镍。随后，在开口内和焊料润湿材料之上提供焊料。

9. 发明申请

US20070138529A1 MIS capacitor and method of formation 有权
标题翻译： MIS电容器和形成方法
公开(公告)号：US20070138529A1
公开(公告)日：2007-06-21
申请号：US11545481
申请日：2006-10-11
申请人： Cem Basceri , Garo Derderian
发明人： Cem Basceri , Garo Derderian
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L27/10852 , H01L28/55 , H01L28/84 , H01L28/91 , H01L29/94
摘要： An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
摘要翻译：公开了具有低泄漏和高电容的MIS电容器。形成半球状晶粒多晶硅层（HSG）作为下电极。在电介质形成之前，半球状晶粒多晶硅层可以任选地进行氮化或退火工艺。在半球形颗粒上制造氧化铝（Al 2 O 3 3）的介电层或氧化铝和其它金属氧化物电介质材料的交错层的复合叠层多晶硅层和可选的氮化或退火工艺后。氧化铝（Al 2 O 3 3）的电介质层或氧化铝复合叠层可以任选地进行后沉积处理以进一步增加电容并减小漏电流。通过沉积技术或通过原子层沉积在电介质层或复合叠层上形成金属氮化物上电极。

10. 发明申请

US20070063262A1 NAND memory arrays 审中-公开
标题翻译： NAND存储器阵列
公开(公告)号：US20070063262A1
公开(公告)日：2007-03-22
申请号：US11601095
申请日：2006-11-17
申请人： Michael Violette , Garo Derderian , Todd Abbott
发明人： Michael Violette , Garo Derderian , Todd Abbott
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11526 , H01L27/11529 , Y10S438/981
摘要： A NAND memory array has a plurality of rows of memory cells and a plurality of columns of NAND strings of memory cells. Each NAND string is selectively connected to a bit line through a drain select gate of the respective column. Each of the drain select gates has a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer. Each of the memory cells of each of the NAND strings has a second dielectric layer formed on the substrate adjacent the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer. The first dielectric layer is thicker than the second dielectric layer.
摘要翻译： NAND存储器阵列具有多行存储器单元和多列存储器单元的NAND串。每个NAND串通过相应列的漏极选择栅选择性地连接到位线。每个漏极选择栅极具有形成在存储器阵列的半导体衬底上的第一电介质层和形成在第一介电层上的控制栅极。每个NAND串的每个存储单元具有形成在与第一介电层相邻的基板上的第二介质层，形成在第二介电层上的浮动栅极，形成在浮置栅极上的第三介电层，以及控制栅极形成在第三电介质层上。第一电介质层比第二电介质层厚。

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