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1. 发明授权

US06359824B1 Activation of wordline decoders to transfer a high voltage supply 有权
标题翻译：激活字线解码器传输高压电源
公开(公告)号：US06359824B1
公开(公告)日：2002-03-19
申请号：US09592474
申请日：2000-06-09
申请人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
发明人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/08
摘要： The present invention discloses a method and system for activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in a memory device. A plurality of wordline voltage supply circuits supply voltage for the wordlines. During operation, when the memory device is placed in a test mode requiring application of the predetermined high voltage to the wordlines, the wordline decoder circuits are activated. In addition, a first predetermined voltage that is approximately zero volts is supplied by the wordline voltage supply circuits to the wordline decoder circuits for a first predetermined amount of time. Once the wordline decoder circuits decode the respective wordlines, the first predetermined voltage is transferred to the respective wordlines. The wordline voltage supply circuits then supply a second predetermined voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a second predetermined amount of time. Finally, the wordline voltage supply circuits supply a predetermined high voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a third predetermined amount of time.
摘要翻译：本发明公开了一种用于激活多个字线解码器电路以在存储器件中的测试模式期间将预定高电压传送到多个字线的方法和系统。多个字线电压电路为字线提供电压。在操作期间，当存储器件被放置在需要对字线施加预定高电压的测试模式时，字线解码器电路被激活。此外，大约零伏特的第一预定电压由字线电压供应电路在第一预定时间量内被提供给字线解码器电路。一旦字线解码器电路解码相应的字线，则第一预定电压被传送到相应的字线。然后，字线电压供应电路提供第二预定电压，该第二预定电压由静止激活的字线解码器电路传送到相应的字线第二预定时间量。最后，字线电压供给电路通过静止激活的字线解码器电路提供预定的高电压，该预定的高电压被传送到相应的字线第三预定的时间量。

2. 发明授权

US06587982B1 Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling 失效
标题翻译：双机状态机与测试仪接口之间的界面的微架构实现方法，以实现双轨循环
公开(公告)号：US06587982B1
公开(公告)日：2003-07-01
申请号：US09654965
申请日：2000-09-05
申请人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
发明人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
IPC分类号： G01R3128
CPC分类号： G01R31/31724 , G01R31/3187 , G11C29/1201 , G11C29/16 , G11C29/48
摘要： There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.
摘要翻译：提供了一种用于BIST状态机的测试器接口电路和用于微结构实现的方法，以便能够通过BIST测试循环。测试器接口电路包括存储设备，逻辑解码器，集合/清除机制和轮询逻辑设备。测试器接口电路在半导体IC上以最小量的芯片面积实现。

3. 发明授权

US6118694A Distributing CFI devices in existing decoders 有权
标题翻译：在现有解码器中分配CFI设备
公开(公告)号：US6118694A
公开(公告)日：2000-09-12
申请号：US417731
申请日：1999-10-14
申请人： Colin S. Bill , Feng Pan
发明人： Colin S. Bill , Feng Pan
IPC分类号： G11C7/10 , G11C8/10 , G11C11/4096 , G11C14/00
CPC分类号： G11C8/10 , G11C11/4096 , G11C7/1048
摘要： The present invention discloses a CFI bit line decoder for a memory device that is capable of storing common flash interface data. In the preferred embodiment, the CFI bit line decoder has at least one bit line decoder circuit including at least one pass gate and a plurality of bit line pass gates, wherein each pass gate is electrically connected with at least one pass gate. In addition, the CFI bit line decoder includes at least one CFI storage circuit that has at least one storage cell electrically connected with the bit line decoder circuit. Each storage cell is in turn electrically connected with the bit line pass gate of the bit line decoder circuit. During CFI mode, a vertical address signal is used to enable a respective pass gate and a CFI address signal is used to enable a respective storage cell. A read circuit is then used to sense the logic state of the storage cell so that a peripheral device can use the data.
摘要翻译：本发明公开了一种能够存储公共闪存接口数据的存储器件的CFI位线解码器。在优选实施例中，CFI位线解码器具有至少一个位线解码器电路，其包括至少一个传输门和多个位线传输门，其中每个传输门与至少一个传输门电连接。此外，CFI位线解码器包括至少一个CFI存储电路，其具有与位线解码器电路电连接的至少一个存储单元。每个存储单元又与位线解码器电路的位线传输门电连接。在CFI模式期间，使用垂直地址信号来使能相应的通过门，并且使用CFI地址信号使能相应的存储单元。然后，读取电路用于感测存储单元的逻辑状态，使得外围设备可以使用数据。

4. 发明授权

US06622274B1 Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization 失效
标题翻译：采用“死亡逻辑”状态转换进行区域最小化的双向前置状态机的微架构实现方法
公开(公告)号：US06622274B1
公开(公告)日：2003-09-16
申请号：US09655335
申请日：2000-09-05
申请人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista
发明人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista
IPC分类号： G11C2900
CPC分类号： G11C29/16 , G01R31/3187
摘要： There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I.C. chip area was realized in comparison to the implementation by a conventional state machine.
摘要翻译：提供了一种改进的BIST前端状态机和用于微结构实现的方法，其通过最少量的测试逻辑电路来实现。状态前端机器包括响应于时钟信号的状态控制器，控制信号和输出寄存器信号，用于基于使用死亡逻辑的固定数量的状态来产生输出状态信号，以便通过多组测试中的一个来完成，直到完成或失败。在国际劳工组织大幅节省约40％与常规状态机的实现相比，实现了芯片面积。

5. 发明授权

US06205056B1 Automated reference cell trimming verify 失效
标题翻译：自动参考细胞修剪验证
公开(公告)号：US06205056B1
公开(公告)日：2001-03-20
申请号：US09524897
申请日：2000-03-14
申请人： Feng Pan , Colin S. Bill
发明人： Feng Pan , Colin S. Bill
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.
摘要翻译：提供了一种参考修整验证电路和方法，用于对闪存EEPROM存储单元阵列中的参考单元晶体管执行编程验证操作。参考电流分支用于产生对应于要编程的参考单元的预定过驱动电压的参考电流。漏极电流分支耦合到待编程的参考单元晶体管，并且当漏极电流处于期望电平时，以施加到其控制栅极的固定栅极电压和施加到其漏极的预定漏极电压产生漏极电流。比较器用于比较对应于漏极电流的感测电压和对应于参考电流的参考电压。当感测到的电压小于参考电压并且当感测的电压大于参考电压时，比较器产生处于低逻辑电平的输出信号，并且其处于高逻辑电平。每当比较器产生低逻辑电平时，将编程脉冲施加到参考晶体管，并在比较器产生高逻辑电平时终止编程脉冲。

6. 发明授权

US07355886B1 Method of programming, erasing and reading memory cells in a resistive memory array 有权
标题翻译：在电阻式存储器阵列中编程，擦除和读取存储单元的方法
公开(公告)号：US07355886B1
公开(公告)日：2008-04-08
申请号：US11633791
申请日：2006-12-05
申请人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
发明人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.
摘要翻译：本方法是将数据写入（其可以是编程或擦除）数据到存储器阵列的选定存储单元的方法。阵列包括多个字线，多个位线，多个存储单元，每个存储单元包括串联连接字线和位线的二极管和电阻存储器件，以及多个晶体管，每个晶体管具有第一和第二源极/漏极端子和栅极，每个晶体管具有连接到位线的第一源极/漏极端子。在本方法中，对所选择的字线施加电压，并且将电压施加到其第一源极/漏极端子连接到选定位线的晶体管的第二源极/漏极端子。施加到所选字线的电压大于施加到该晶体管的第二源极/漏极端子的电压。

7. 发明授权

US07145824B2 Temperature compensation of thin film diode voltage threshold in memory sensing circuit 有权
标题翻译：存储器感应电路中薄膜二极管电压阈值的温度补偿
公开(公告)号：US07145824B2
公开(公告)日：2006-12-05
申请号：US11086884
申请日：2005-03-22
申请人： Colin S. Bill , Wei Daisy Cai
发明人： Colin S. Bill , Wei Daisy Cai
IPC分类号： G11C7/04
CPC分类号： G11C13/0016 , B82Y10/00 , G11C7/04 , G11C11/5664 , G11C13/00 , G11C13/0014 , G11C2213/72 , Y10S977/943
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.
摘要翻译：提供了用于存储器感测电路中的薄膜二极管电压电平的温度补偿的系统和方法。本发明包括温度敏感偏置电路和具有温度可变选择装置的阵列芯。阵列芯可以由与纳米级电阻式存储单元串联的薄膜二极管组成。温度敏感偏置电路可以包括与两个电阻器串联的薄膜二极管，并且向阵列芯提供温度补偿偏置电压。温度敏感偏置电路的薄膜二极管跟踪阵列芯的二极管，而两个电阻产生电阻比，以模拟阵列芯上的温度和/或工艺变化的影响。补偿偏置参考电压由温度敏感偏置电路产生，由差分放大器复制，并用于在纳米级电阻存储单元上维持恒定的工作电压电平。

8. 发明授权

US06449190B1 Adaptive reference cells for a memory device 有权
标题翻译：用于存储器件的自适应参考单元
公开(公告)号：US06449190B1
公开(公告)日：2002-09-10
申请号：US09764965
申请日：2001-01-17
申请人： Colin S. Bill
发明人： Colin S. Bill
IPC分类号： G11C1600
CPC分类号： G11C16/28
摘要： A memory device is provided with reference cells that can be adapted to the core cells of the memory device. An erase verify reference cell. is adapted to the core cells by changing the threshold voltage of the erase verify reference cell until substantially all the core cells pass an erase verification test. A program verify reference cell is then setup by changing the threshold voltage of the program reference cell by a desired change in voltage between erased and programmed states. A read reference cell is also setup by changing the threshold voltage of the read reference cell so that it is intermediate of the erase verify reference cell and the program verify reference cell.
摘要翻译：存储器装置设置有可适应存储器件的核心单元的参考单元。擦除验证参考单元。通过改变擦除验证参考单元的阈值电压直到基本上所有的核心单元通过擦除验证测试来适应核心单元。然后通过将程序参考单元的阈值电压改变为擦除和编程状态之间的期望的电压变化来建立程序验证参考单元。读取参考单元也通过改变读取的参考单元的阈值电压来设置，使得它是擦除验证参考单元和程序验证参考单元的中间。

9. 发明授权

US06430087B1 Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage 有权
标题翻译：用于字线增强器的修整方法和系统，以最大限度地减少提升字线电压的工艺变化
公开(公告)号：US06430087B1
公开(公告)日：2002-08-06
申请号：US09547660
申请日：2000-04-12
申请人： Colin S. Bill , Ravi P. Gutala
发明人： Colin S. Bill , Ravi P. Gutala
IPC分类号： G11C1600
CPC分类号： G11C16/08 , G11C5/145 , G11C8/08
摘要： A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster in a wordline voltage booster circuit. An adjustable clamp circuit is electrically connected with the wordline voltage booster circuit for clamping the gate voltage that is generated by the voltage booster at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit that is electrically connected to the adjustable clamp circuit, depending on process variations experienced during fabrication by the adjustable clamp circuit.
摘要翻译：通过本发明公开了一种用于控制在闪速存储器中的读取操作期间使用的升压的字线电压的方法和系统。在优选实施例中，栅极电压由字线升压电路中的升压器产生。可调式钳位电路与字线升压电路电连接，用于将由升压器产生的栅极电压钳位在预定电压电平。可以根据可调节钳位电路制造过程中经历的过程变化，利用与可调节钳位电路电连接的微调电路来调整预定电压电平。

10. 发明授权

US07894243B2 Methods of programming and erasing resistive memory devices 有权
标题翻译：编程和擦除电阻式存储器件的方法
公开(公告)号：US07894243B2
公开(公告)日：2011-02-22
申请号：US11633800
申请日：2006-12-05
申请人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
发明人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32
摘要： In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.
摘要翻译：在将数据写入电阻存储器件（即编程或擦除）的第一种方法中，连续电势被施加在电阻性存储器件上，其中连续的电势具有增加的持续时间。在将数据写入电阻式存储器件（即编程或擦除）的另一种方法中，在电阻性存储器件上施加电势，并且在施加电位时感测通过存储器件的电流。电位的施加基于通过电阻式存储器件的选定电流水平而结束。

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