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1. 发明授权

US06587982B1 Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling 失效
标题翻译：双机状态机与测试仪接口之间的界面的微架构实现方法，以实现双轨循环
公开(公告)号：US06587982B1
公开(公告)日：2003-07-01
申请号：US09654965
申请日：2000-09-05
申请人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
发明人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista , Azrul Halim
IPC分类号： G01R3128
CPC分类号： G01R31/31724 , G01R31/3187 , G11C29/1201 , G11C29/16 , G11C29/48
摘要： There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.
摘要翻译：提供了一种用于BIST状态机的测试器接口电路和用于微结构实现的方法，以便能够通过BIST测试循环。测试器接口电路包括存储设备，逻辑解码器，集合/清除机制和轮询逻辑设备。测试器接口电路在半导体IC上以最小量的芯片面积实现。

2. 发明授权

US06622274B1 Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization 失效
标题翻译：采用“死亡逻辑”状态转换进行区域最小化的双向前置状态机的微架构实现方法
公开(公告)号：US06622274B1
公开(公告)日：2003-09-16
申请号：US09655335
申请日：2000-09-05
申请人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista
发明人： Weng F. Lee , Colin S. Bill , Feng Pan , Edward V. Bautista
IPC分类号： G11C2900
CPC分类号： G11C29/16 , G01R31/3187
摘要： There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I.C. chip area was realized in comparison to the implementation by a conventional state machine.
摘要翻译：提供了一种改进的BIST前端状态机和用于微结构实现的方法，其通过最少量的测试逻辑电路来实现。状态前端机器包括响应于时钟信号的状态控制器，控制信号和输出寄存器信号，用于基于使用死亡逻辑的固定数量的状态来产生输出状态信号，以便通过多组测试中的一个来完成，直到完成或失败。在国际劳工组织大幅节省约40％与常规状态机的实现相比，实现了芯片面积。

3. 发明授权

US07057949B1 Method and apparatus for pre-charging negative pump MOS regulation capacitors 失效
标题翻译：负电泵MOS调节电容器预充电方法和装置
公开(公告)号：US07057949B1
公开(公告)日：2006-06-06
申请号：US10050342
申请日：2002-01-16
申请人： Feng Pan , Weng Fook Lee , Edward V. Bautista, Jr. , Santosh K. Yachareni
发明人： Feng Pan , Weng Fook Lee , Edward V. Bautista, Jr. , Santosh K. Yachareni
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C16/30
摘要： Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.
摘要翻译：公开了用于在半导体存储器件中使用负栅极电压擦除核心存储器单元的方法和装置，其中在核心单元擦除操作期间，根据预充电信号对负泵MOS调节电容器进行预充电。然后使用预充电的负泵MOS调节电容器调节负电压泵，以提供负栅极电压。公开了一种用于在存储器件中的核心单元擦除操作期间对负泵MOS调节电容器预充电的装置，其包括连接在参考电压和负泵MOS调节电容器之间的开关，以及提供预充电的预充电控制电路充电信号到开关，以选择性地将参考电压连接到负泵MOS调节电容器，以在擦除操作中对其进行预充电。

4. 发明授权

US06385093B1 I/O partitioning system and methodology to reduce band-to-band tunneling current during erase 有权
标题翻译： I / O分区系统和方法，以减少擦除期间的带 - 带隧穿电流
公开(公告)号：US06385093B1
公开(公告)日：2002-05-07
申请号：US09822995
申请日：2001-03-30
申请人： Edward V. Bautista, Jr. , Kazuhiro Kurihara , Feng Pan , Weng Fook Lee , Ravi Sunkavalli , Darlene Hamilton
发明人： Edward V. Bautista, Jr. , Kazuhiro Kurihara , Feng Pan , Weng Fook Lee , Ravi Sunkavalli , Darlene Hamilton
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.
摘要翻译：提供了一种用于在闪速存储器擦除操作期间减少带对隧道电流的系统。该系统包括分为（N）I / O子部分，N为整数的存储器扇区和用于在N I / O子部门内产生用于相关联的擦除操作的功率的排水泵。擦除排序子系统产生N个脉冲，以便能够在每个N I / O子部件内进行擦除操作，以便减少由排水泵提供的带间隧穿电流。

5. 发明授权

US6118694A Distributing CFI devices in existing decoders 有权
标题翻译：在现有解码器中分配CFI设备
公开(公告)号：US6118694A
公开(公告)日：2000-09-12
申请号：US417731
申请日：1999-10-14
申请人： Colin S. Bill , Feng Pan
发明人： Colin S. Bill , Feng Pan
IPC分类号： G11C7/10 , G11C8/10 , G11C11/4096 , G11C14/00
CPC分类号： G11C8/10 , G11C11/4096 , G11C7/1048
摘要： The present invention discloses a CFI bit line decoder for a memory device that is capable of storing common flash interface data. In the preferred embodiment, the CFI bit line decoder has at least one bit line decoder circuit including at least one pass gate and a plurality of bit line pass gates, wherein each pass gate is electrically connected with at least one pass gate. In addition, the CFI bit line decoder includes at least one CFI storage circuit that has at least one storage cell electrically connected with the bit line decoder circuit. Each storage cell is in turn electrically connected with the bit line pass gate of the bit line decoder circuit. During CFI mode, a vertical address signal is used to enable a respective pass gate and a CFI address signal is used to enable a respective storage cell. A read circuit is then used to sense the logic state of the storage cell so that a peripheral device can use the data.
摘要翻译：本发明公开了一种能够存储公共闪存接口数据的存储器件的CFI位线解码器。在优选实施例中，CFI位线解码器具有至少一个位线解码器电路，其包括至少一个传输门和多个位线传输门，其中每个传输门与至少一个传输门电连接。此外，CFI位线解码器包括至少一个CFI存储电路，其具有与位线解码器电路电连接的至少一个存储单元。每个存储单元又与位线解码器电路的位线传输门电连接。在CFI模式期间，使用垂直地址信号来使能相应的通过门，并且使用CFI地址信号使能相应的存储单元。然后，读取电路用于感测存储单元的逻辑状态，使得外围设备可以使用数据。

6. 发明授权

US06205056B1 Automated reference cell trimming verify 失效
标题翻译：自动参考细胞修剪验证
公开(公告)号：US06205056B1
公开(公告)日：2001-03-20
申请号：US09524897
申请日：2000-03-14
申请人： Feng Pan , Colin S. Bill
发明人： Feng Pan , Colin S. Bill
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.
摘要翻译：提供了一种参考修整验证电路和方法，用于对闪存EEPROM存储单元阵列中的参考单元晶体管执行编程验证操作。参考电流分支用于产生对应于要编程的参考单元的预定过驱动电压的参考电流。漏极电流分支耦合到待编程的参考单元晶体管，并且当漏极电流处于期望电平时，以施加到其控制栅极的固定栅极电压和施加到其漏极的预定漏极电压产生漏极电流。比较器用于比较对应于漏极电流的感测电压和对应于参考电流的参考电压。当感测到的电压小于参考电压并且当感测的电压大于参考电压时，比较器产生处于低逻辑电平的输出信号，并且其处于高逻辑电平。每当比较器产生低逻辑电平时，将编程脉冲施加到参考晶体管，并在比较器产生高逻辑电平时终止编程脉冲。

7. 发明授权

US06359824B1 Activation of wordline decoders to transfer a high voltage supply 有权
标题翻译：激活字线解码器传输高压电源
公开(公告)号：US06359824B1
公开(公告)日：2002-03-19
申请号：US09592474
申请日：2000-06-09
申请人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
发明人： Colin S. Bill , Jonathan Shi-Chang Su , Feng Pan
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/08
摘要： The present invention discloses a method and system for activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in a memory device. A plurality of wordline voltage supply circuits supply voltage for the wordlines. During operation, when the memory device is placed in a test mode requiring application of the predetermined high voltage to the wordlines, the wordline decoder circuits are activated. In addition, a first predetermined voltage that is approximately zero volts is supplied by the wordline voltage supply circuits to the wordline decoder circuits for a first predetermined amount of time. Once the wordline decoder circuits decode the respective wordlines, the first predetermined voltage is transferred to the respective wordlines. The wordline voltage supply circuits then supply a second predetermined voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a second predetermined amount of time. Finally, the wordline voltage supply circuits supply a predetermined high voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a third predetermined amount of time.
摘要翻译：本发明公开了一种用于激活多个字线解码器电路以在存储器件中的测试模式期间将预定高电压传送到多个字线的方法和系统。多个字线电压电路为字线提供电压。在操作期间，当存储器件被放置在需要对字线施加预定高电压的测试模式时，字线解码器电路被激活。此外，大约零伏特的第一预定电压由字线电压供应电路在第一预定时间量内被提供给字线解码器电路。一旦字线解码器电路解码相应的字线，则第一预定电压被传送到相应的字线。然后，字线电压供应电路提供第二预定电压，该第二预定电压由静止激活的字线解码器电路传送到相应的字线第二预定时间量。最后，字线电压供给电路通过静止激活的字线解码器电路提供预定的高电压，该预定的高电压被传送到相应的字线第三预定的时间量。

8. 外观设计

USD968154S1 Toaster 有权
公开(公告)号：USD968154S1
公开(公告)日：2022-11-01
申请号：US29837797
申请日：2022-05-09
申请人： Feng Pan
设计人： Feng Pan

9. 发明授权

US09313504B2 Pattern detection module with region detection, video encoding system and method for use therewith 有权
标题翻译：具有区域检测的图案检测模块，视频编码系统及其使用方法
公开(公告)号：US09313504B2
公开(公告)日：2016-04-12
申请号：US12254586
申请日：2008-10-20
申请人： Feng Pan , Jingyun Jiao , Yang Liu
发明人： Feng Pan , Jingyun Jiao , Yang Liu
IPC分类号： G06F21/00 , H04N19/115 , H04N19/46 , H04N19/61 , H04N19/14 , H04N19/186 , H04N19/17 , H04N19/40
CPC分类号： H04N19/115 , H04N19/14 , H04N19/17 , H04N19/186 , H04N19/40 , H04N19/46 , H04N19/61
摘要： A system for encoding a video stream into a processed video signal that includes at least one image, includes a pattern detection module for detecting a pattern of interest in the at least one image and identifying a region that contains the pattern of interest when the pattern of interest is detected, based on an analysis of the image in a plurality of domains. An encoder section, generates the processed video signal and wherein, when the pattern of interest is detected, a higher quality, such as a higher bit allocation or higher computational processing, is assigned to the region than to portions of the at least one image outside the region.
摘要翻译：一种用于将视频流编码成包括至少一个图像的经处理的视频信号的系统，包括：图案检测模块，用于在所述至少一个图像中检测感兴趣的图案，并且当所述图案的图案被识别时，识别包含感兴趣图案的区域; 基于对多个域中的图像的分析来检测兴趣。编码器部分生成经处理的视频信号，并且其中，当检测到感兴趣的图案时，将更高的质量（例如较高的位分配或更高的计算处理）分配给该区域而不是至少一个图像外部的部分该区域。

10. 发明授权

US08737125B2 Aggregating data latches for program level determination 有权
标题翻译：汇总数据锁存器进行程序级确定
公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

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