专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06972220B2 Structures and methods of anti-fuse formation in SOI 失效
标题翻译： SOI中抗熔丝形成的结构和方法
公开(公告)号：US06972220B2
公开(公告)日：2005-12-06
申请号：US10366298
申请日：2003-02-12
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L21/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

2. 发明授权

US06596592B2 Structures and methods of anti-fuse formation in SOI 失效
公开(公告)号：US06596592B2
公开(公告)日：2003-07-22
申请号：US10066759
申请日：2002-02-06
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

3. 发明授权

US07226816B2 Method of forming connection and anti-fuse in layered substrate such as SOI 有权
标题翻译：在诸如SOI的层状衬底中形成连接和反熔丝的方法
公开(公告)号：US07226816B2
公开(公告)日：2007-06-05
申请号：US11055106
申请日：2005-02-11
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

4. 发明授权

US06396121B1 Structures and methods of anti-fuse formation in SOI 失效
公开(公告)号：US06396121B1
公开(公告)日：2002-05-28
申请号：US09583468
申请日：2000-05-31
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

5. 发明授权

US06790722B1 Logic SOI structure, process and application for vertical bipolar transistor 有权
标题翻译：逻辑SOI结构，工艺和应用于垂直双极晶体管
公开(公告)号：US06790722B1
公开(公告)日：2004-09-14
申请号：US09718850
申请日：2000-11-22
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L29/66265 , H01L21/8249 , H01L27/0623 , H01L29/7317
摘要： A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
摘要翻译：用于在垂直双极晶体管中形成发射极的方法和结构包括在集电极层上提供具有集电极层和基极层的衬底，在集电极层上形成图案掩模，并在发光体材料中填充掩模中的开口大马士革过程。 CMOS /垂直双极结构具有彼此垂直设置的集电极，基极区域和发射极区域，集电极区域具有与衬底间隔离氧化物相邻的峰值掺杂剂浓度。

6. 发明授权

US06492211B1 Method for novel SOI DRAM BICMOS NPN 失效
标题翻译：新型SOI DRAM BICMOS NPN的方法
公开(公告)号：US06492211B1
公开(公告)日：2002-12-10
申请号：US09656819
申请日：2000-09-07
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , W. David Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , W. David Pricer , William R. Tonti
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , G11C7/065 , G11C2207/005 , G11C2207/065 , H01L21/84 , H01L27/10861 , H01L27/10897 , H01L27/1203
摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.
摘要翻译：在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。使用NFET的DRAM阵列允许集成双极NPN序列。类似地，通过将阵列晶体管改变为PFET来实现垂直双极PNP器件。特别地，在SOI中制造BICMOS器件。双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

7. 发明授权

US06420749B1 Trench field shield in trench isolation 失效
标题翻译：沟槽隔离屏蔽沟槽
公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译：一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。第一装置可以独立于第二装置而被偏置。接触件在衬底的表面上方延伸。第一接触件邻接第一器件和第一导电侧壁间隔物。绝缘体将导电侧墙隔离开。第一接触件可以在第一导体和第二导体之间等距。导电侧壁间隔件包括场屏蔽。

8. 发明授权

US06274441B1 Method of forming bitline diffusion halo under gate conductor ledge 失效
标题翻译：在栅极导体突起处形成位线扩散晕的方法
公开(公告)号：US06274441B1
公开(公告)日：2001-08-14
申请号：US09560073
申请日：2000-04-27
申请人： Jack A. Mandelman , Ramachandra Divakaruni , William R. Tonti
发明人： Jack A. Mandelman , Ramachandra Divakaruni , William R. Tonti
IPC分类号： H01L2170
CPC分类号： H01L29/1045 , H01L21/266 , H01L27/10861 , H01L27/10873 , H01L27/10888 , H01L29/1083 , H01L29/6653 , H01L29/66659
摘要： A method for fabricating a MOSFET device including a halo implant comprising providing a semiconductor substrate, a gate insulator layer, a conductor layer, an overlying silicide layer, and an insulating cap; patterning and etching the silicide layer and the insulating cap; providing insulating spacers along sides of said silicide layer and insulating cap; implanting node and bitline N+ diffusion regions; patterning a photoresist layer to protect the node diffusion region and supporting PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; etching exposed spacer material from the side of said silicide layer and insulating cap; implanting a P-type impurity halo implant into the exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulating spacer along the exposed side of said silicide layer and insulating cap.
摘要翻译：一种制造包括卤素注入的MOSFET器件的方法，包括提供半导体衬底，栅极绝缘体层，导体层，上覆硅化物层和绝缘帽; 图案化和蚀刻硅化物层和绝缘帽; 在所述硅化物层和绝缘盖的侧面提供绝缘垫片; 植入节点和位线N +扩散区域; 图案化光致抗蚀剂层以保护节点扩散区域并支持PFET源极和漏极区域并暴露位线扩散区域和NFET源极和漏极区域; 从所述硅化物层和绝缘盖的侧面蚀刻暴露的间隔物材料; 将P型杂质卤素注入植入暴露的位线扩散区并支持NFET源极和漏极区; 并剥离光致抗蚀剂层，并沿着所述硅化物层和绝缘帽的暴露侧提供绝缘间隔物。

9. 发明授权

US06518641B2 Deep slit isolation with controlled void 失效
标题翻译：深狭缝隔离带受控空隙
公开(公告)号：US06518641B2
公开(公告)日：2003-02-11
申请号：US09861274
申请日：2001-05-18
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Johnathan E. Faltermeier , William R. Tonti
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Johnathan E. Faltermeier , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L21/76232 , H01L21/764
摘要： An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.
摘要翻译：一种用于存储器阵列的隔离区域，其中隔离区域包括至少一个具有延伸到底表面的侧壁和形成在最终沟槽区域下方的狭缝区域的沟槽区域，其中狭缝区域比上覆沟槽区域窄，并且具有提供了有意形成的空隙。

10. 发明授权

US06150212A Shallow trench isolation method utilizing combination of spacer and fill 失效
标题翻译：使用间隔物和填充物的组合的浅沟槽隔离方法
公开(公告)号：US06150212A
公开(公告)日：2000-11-21
申请号：US359287
申请日：1999-07-22
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232 , H01L27/10861 , H01L27/1087
摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要翻译：一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面底面并形成缝隙区域。间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式