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    • 3. 发明申请
    • Methods and Apparatus for Sensing Organic Tissue
    • 用于感应有机组织的方法和装置
    • US20130162459A1
    • 2013-06-27
    • US13337472
    • 2011-12-27
    • Nadav AharonyMichael Siegel
    • Nadav AharonyMichael Siegel
    • G01S13/02
    • G01S13/003G01S11/02G01S13/04
    • In exemplary implementations of this invention, a radio signal is transmitted between a transmitter and a receiver. Either the transmitter, or receiver, or both, have a directional antenna. When organic tissue passes between (or is stationary between) the transmitter and receiver, the tissue causes a reduction of the received signal strength (RSS) of the signal, as compared to a baseline RSS. The larger the amount of tissue, the greater is the reduction of the RSS. By analyzing the degradation of the signal, information about organic tissue between the transmitter and receiver may be determined. For example, the number of persons passing through a physical threshold may be determined. Or the fact that one person is walking faster than, and catching up with, a second person as they pass between the transmitter and receiver may be determined.
    • 在本发明的示例性实现中,在发射机和接收机之间传送无线电信号。 发射机或接收机或两者都具有定向天线。 当有机组织在发射器和接收器之间通过(或者在其之间)时,与基线RSS相比,组织导致信号的接收信号强度(RSS)的降低。 组织量越大,RSS的减少就越大。 通过分析信号的劣化,可以确定关于发射机和接收机之间的有机组织的信息。 例如,可以确定通过物理阈值的人数。 或者一个人在发射机和接收机之间通过的情况下,第二人可以确定一个人比行进速度更快,并且追赶的事实。
    • 4. 发明申请
    • System and method for exchanging messages in a multi-processor environment
    • 用于在多处理器环境中交换消息的系统和方法
    • US20070033303A1
    • 2007-02-08
    • US11198042
    • 2005-08-05
    • Jeffrey BridgesGordon DavisThomas SartoriusMichael Siegel
    • Jeffrey BridgesGordon DavisThomas SartoriusMichael Siegel
    • G06F13/28
    • G06F13/28
    • A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.
    • 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中,以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时,创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接,使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。
    • 6. 发明申请
    • APPARATUS AND METHOD FOR OPERATING AN APPARATUS FOR DETERMINING AND/OR MONITORING AT LEAST ONE PHYSICAL PROCESS VARIABLE
    • 用于确定和/或监控至少一个物理过程可变的装置和方法
    • US20120279283A1
    • 2012-11-08
    • US13462933
    • 2012-05-03
    • Tobias BrengartnerMartin UrbanMichael Siegel
    • Tobias BrengartnerMartin UrbanMichael Siegel
    • G01H13/00G01F23/22G01F1/78G01N11/16
    • G01F23/2961G01F23/2965G01F23/2967
    • A method for operating an apparatus which has an oscillatable unit. The oscillatable unit is excited to oscillate by means of a first frequency sweep within a predetermined frequency band with successive, discrete exciter frequencies of increasing or decreasing frequency. A first exciter frequency is ascertained, in the case of which, during the first frequency sweep, at least one predeterminable criterion is fulfilled. The oscillatable unit is excited by means of a second frequency sweep, wherein the frequency band, compared with the first frequency sweep, is run through in the opposite direction. A second exciter frequency is ascertained, in the case of which, during the second frequency sweep, the at least one predeterminable criterion is fulfilled. From the first exciter frequency and the second exciter frequency, via formation of an average, a measuring frequency for determining and/or monitoring at least one process variable is determined.
    • 一种用于操作具有可振荡单元的装置的方法。 振荡单元被激励以借助于具有递增或递减频率的连续的离散激励器频率在预定频带内的第一频率扫描振荡。 确定第一激励器频率,在第一次频率扫描的情况下,满足至少一个可预定标准。 可振荡单元通过第二频率扫描来激励,其中与第一频率扫描相比,频带沿相反方向穿过。 确定第二激励器频率,在第二频率扫描的情况下,满足至少一个可预定标准。 通过形成平均值,从第一激励器频率和第二激励器频率确定用于确定和/或监视至少一个过程变量的测量频率。
    • 10. 发明授权
    • Virtual barrier synchronization cache castout election
    • 虚拟屏障同步缓存突发选举
    • US08095733B2
    • 2012-01-10
    • US12419343
    • 2009-04-07
    • Ravi K. ArimilliGuy L. GuthrieMichael SiegelWilliam J. StarkeDerek E. Williams
    • Ravi K. ArimilliGuy L. GuthrieMichael SiegelWilliam J. StarkeDerek E. Williams
    • G06F13/00G06F13/28
    • G06F12/0811G06F9/30101G06F9/3851G06F9/522
    • A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
    • 数据处理系统包括互连结构,耦合到互连结构并包括分配给虚拟屏障同步寄存器(VBSR)的存储的虚拟屏障同步区域的系统存储器,以及耦合到互连结构的多个处理单元, 访问虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器,其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。 响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路, 第二和第三处理单元。 通过互连结构上的选举来转移责任。