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1. 发明授权

US07169675B2 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US07169675B2
公开(公告)日：2007-01-30
申请号：US10886442
申请日：2004-07-07
申请人： Chung Foong Tan , Jinping Liu , Hyeokjae Lee , Kheng Chok Tee , Elgin Quek
发明人： Chung Foong Tan , Jinping Liu , Hyeokjae Lee , Kheng Chok Tee , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

2. 发明授权

US07071069B2 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US07071069B2
公开(公告)日：2006-07-04
申请号：US10743247
申请日：2003-12-22
申请人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
发明人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

3. 发明申请

US20070117326A1 MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR 审中-公开
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20070117326A1
公开(公告)日：2007-05-24
申请号：US11625789
申请日：2007-01-22
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083 , H01L29/6659
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

4. 发明申请

US20060006427A1 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20060006427A1
公开(公告)日：2006-01-12
申请号：US10886442
申请日：2004-07-07
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

5. 发明授权

US07998835B2 Strain-direct-on-insulator (SDOI) substrate and method of forming 有权
标题翻译：绝缘体绝缘体（SDOI）基板及其成型方法
公开(公告)号：US07998835B2
公开(公告)日：2011-08-16
申请号：US12008841
申请日：2008-01-15
申请人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
发明人： Lee Wee Teo , Chung Foong Tan , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/165 , H01L21/76254 , H01L29/1054 , Y10S438/933
摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.
摘要翻译：描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。绝缘体邻近最外层应变硅层设置。最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

6. 发明授权

US08748271B2 LDMOS with improved breakdown voltage 有权
标题翻译： LDMOS具有改善的击穿电压
公开(公告)号：US08748271B2
公开(公告)日：2014-06-10
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L29/40 , H01L29/49 , H01L29/78 , H01L29/51 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

7. 发明授权

US08492235B2 FinFET with stressors 有权
公开(公告)号：US08492235B2
公开(公告)日：2013-07-23
申请号：US12980375
申请日：2010-12-29
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/0847 , H01L29/1037 , H01L29/1054 , H01L29/41783 , H01L29/66795 , H01L29/7848 , H01L29/7849
摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

8. 发明授权

US08446779B2 Non-volatile memory using pyramidal nanocrystals as electron storage elements 有权
标题翻译：使用金字塔纳米晶体作为电子存储元件的非易失性存储器
公开(公告)号：US08446779B2
公开(公告)日：2013-05-21
申请号：US12583486
申请日：2009-08-21
申请人： Elgin Quek , Chunshan Yin , Shyue Seng Tan , Jae Gon Lee , Chung Foong Tan
发明人： Elgin Quek , Chunshan Yin , Shyue Seng Tan , Jae Gon Lee , Chung Foong Tan
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/42324 , G11C16/0416 , G11C2216/06 , H01L21/28273 , H01L27/11521 , H01L29/42332
摘要： A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.
摘要翻译：非易失性存储器件包括具有金字塔形的硅纳米晶体作为电子存储元件的浮动栅极。电子从金字塔形的硅纳米晶体通过栅极氧化层隧穿到非易失性存储器件的控制栅极。每个硅纳米晶体的锥体形状在其峰值处集中电场以促进电子隧穿。这允许擦除过程发生在比现有技术的器件更低的隧道电压和更短的隧道时间。

9. 发明申请

US20120038009A1 Novel methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：降低栅极接触电阻的新方法
公开(公告)号：US20120038009A1
公开(公告)日：2012-02-16
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

10. 发明申请

US20120018815A1 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
标题翻译：具有降低的接触电阻的半导体器件及其制造方法
公开(公告)号：US20120018815A1
公开(公告)日：2012-01-26
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

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