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1. 发明申请

US20070045772A1 FUSE STRUCTURE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的保险丝结构
公开(公告)号：US20070045772A1
公开(公告)日：2007-03-01
申请号：US11162150
申请日：2005-08-30
申请人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。保险丝层通过通孔连接到其他金属层。熔丝层包括单独的块和至少一个连接块，并且至少耦合到不同层的热缓冲块。由于热缓冲块耦合到熔丝层的块，所以提供了新的熔点和用于有效散热的新路径，并且通过热缓冲块在块之间获得更长和弯曲的电流路径。加热缓冲块和耦合到热缓冲块的块可以避免大电流流过保险丝结构并防止过热。

2. 发明授权

US07190044B1 Fuse structure for a semiconductor device 有权
标题翻译：一种半导体器件的保险丝结构
公开(公告)号：US07190044B1
公开(公告)日：2007-03-13
申请号：US11162150
申请日：2005-08-30
申请人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Ruey-Chyr Lee , Sheng-Yuan Hsueh
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and bottom insulating layers. The fuse layer is connected to the other metal layers through via plugs. The fuse layer includes separate blocks and at least a connecting block and is coupled to at least a heat buffer block of a different layer. Because the heat buffer block is coupled to the blocks of the fuse layer, new fusing point and a new path for effectively dissipating the heat are provided and a longer and sinuous electric current path is obtained between the blocks through the heat buffer blocks. The heat buffer block and the blocks coupled to the heat buffer block can avoid large current flowing through the fuse structure and prevent overheating.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。保险丝层通过通孔连接到其他金属层。熔丝层包括单独的块和至少一个连接块，并且至少耦合到不同层的热缓冲块。由于热缓冲块耦合到熔丝层的块，所以提供了新的熔点和用于有效散热的新路径，并且通过热缓冲块在块之间获得更长和弯曲的电流路径。加热缓冲块和耦合到热缓冲块的块可以避免大电流流过保险丝结构并防止过热。

3. 发明申请

US20050258504A1 Fuse structure for a semiconductor device 有权
标题翻译：一种半导体器件的保险丝结构
公开(公告)号：US20050258504A1
公开(公告)日：2005-11-24
申请号：US10850201
申请日：2004-05-19
申请人： Chun-Wen Cheng , Chia-Wen Liang , Richard Lee , Vincent Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Richard Lee , Vincent Hsueh
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal layers through the via plugs. The fuse layer includes at least two separate blocks and at least a connecting block. For the current flowing through the separated blocks in a zig-zag path, of the fuse structure provides at least a fusing point or more than one fusing points. In this way, the negative impact of the single failed fuse can be reduced, thus increasing the reliability of the fuse structure. Also the damage to the devices adjacent to the fuse due to the heat generated by the current can be prevented because when the heat generated during the fuse blowing process will be conducted to the adjacent blocks to facilitate heat dissipation.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。熔丝层通过通孔连接到其它金属层。熔丝层包括至少两个单独的块和至少一个连接块。对于流经分隔块的电流，在熔接结构中至少提供一个熔点或多于一个熔点。以这种方式，可以降低单个故障保险丝的负面影响，从而增加了熔丝结构的可靠性。此外，由于当熔丝吹制过程中产生的热量将传导到相邻的块以便于散热时，可以防止由于电流产生的热量而导致与熔断器相邻的器件的损坏。

4. 发明授权

US07176551B2 Fuse structure for a semiconductor device 有权
标题翻译：一种半导体器件的保险丝结构
公开(公告)号：US07176551B2
公开(公告)日：2007-02-13
申请号：US10850201
申请日：2004-05-19
申请人： Chun-Wen Cheng , Chia-Wen Liang , Richard Lee , Vincent Hsueh
发明人： Chun-Wen Cheng , Chia-Wen Liang , Richard Lee , Vincent Hsueh
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal layers through the via plugs. The fuse layer includes at least two separate blocks and at least a connecting block. For the current flowing through the separated blocks in a zig-zag path, of the fuse structure provides at least a fusing point or more than one fusing points. In this way, the negative impact of the single failed fuse can be reduced, thus increasing the reliability of the fuse structure. Also the damage to the devices adjacent to the fuse due to the heat generated by the current can be prevented because when the heat generated during the fuse blowing process will be conducted to the adjacent blocks to facilitate heat dissipation.
摘要翻译：提供一种用于半导体器件的熔丝结构。熔丝结构包括在上绝缘层和下绝缘层之间的熔丝层。熔丝层通过通孔连接到其它金属层。熔丝层包括至少两个单独的块和至少一个连接块。对于流经分隔块的电流，在熔接结构中至少提供一个熔点或多于一个熔点。以这种方式，可以降低单个故障保险丝的负面影响，从而增加了熔丝结构的可靠性。此外，由于当熔丝吹制过程中产生的热量将传导到相邻的块以便于散热时，可以防止由于电流产生的热量而导致与熔断器相邻的器件的损坏。

5. 发明授权

US08674495B2 Package systems having a eutectic bonding material and manufacturing methods thereof 有权
标题翻译：具有共晶接合材料的封装体系及其制造方法
公开(公告)号：US08674495B2
公开(公告)日：2014-03-18
申请号：US13035607
申请日：2011-02-25
申请人： Chia-Pao Shu , Chun-Wen Cheng , Kuei-Sung Chang , Hsin-Ting Huang , Shang-Ying Tsai , Jung-Huei Peng
发明人： Chia-Pao Shu , Chun-Wen Cheng , Kuei-Sung Chang , Hsin-Ting Huang , Shang-Ying Tsai , Jung-Huei Peng
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76838 , B81C1/00238 , B81C1/00269 , B81C2203/019 , H01L23/49838 , H01L23/528 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0362 , H01L2224/04026 , H01L2224/05551 , H01L2224/05555 , H01L2224/05557 , H01L2224/05617 , H01L2224/05638 , H01L2224/061 , H01L2224/08145 , H01L2224/08225 , H01L2224/26145 , H01L2224/29011 , H01L2224/29014 , H01L2224/29017 , H01L2224/2902 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/29117 , H01L2224/29124 , H01L2224/29138 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29181 , H01L2224/301 , H01L2224/32058 , H01L2224/321 , H01L2224/32106 , H01L2224/32148 , H01L2224/83203 , H01L2224/83365 , H01L2224/83805 , H01L2225/06527 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/01014 , H01L2924/01037 , H01L2924/01032 , H01L2924/00 , H01L2924/0132 , H01L2924/00014
摘要： A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.
摘要翻译：封装系统包括第一衬底。第二衬底与第一衬底电耦合。至少一个电接合材料设置在第一基板和第二基板之间。所述至少一个电接合材料包括共晶接合材料。共晶接合材料包括金属材料和半导体材料。金属材料邻近第一基底的表面设置。金属材料包括第一焊盘和围绕第一焊盘的至少一个第一保护环。

6. 发明申请

US20130203199A1 Methods of Bonding Caps for MEMS Devices 有权
标题翻译： MEMS器件封装方法
公开(公告)号：US20130203199A1
公开(公告)日：2013-08-08
申请号：US13365043
申请日：2012-02-02
申请人： Xin-Hua Huang , Ping-Yin Liu , Li-Cheng Chu , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
发明人： Xin-Hua Huang , Ping-Yin Liu , Li-Cheng Chu , Yuan-Chih Hsieh , Lan-Lin Chao , Chun-Wen Cheng , Chia-Shiung Tsai
IPC分类号： H01L21/52 , B23K31/02
CPC分类号： B23K20/002 , B23K20/023
摘要： A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.
摘要翻译：一种方法包括通过共晶接合将第一接合层结合到第二接合层。接合步骤包括将第一接合层和第二接合层加热至高于第一接合层和第二接合层的共晶温度的温度，并进行泵送循环。泵送循环包括施加第一力以将第一接合层和第二接合层相互挤压。在施加第一力的步骤之后，施加比第一力小的第二力以将第一接合层和第二接合层相互挤压。在施加第二力的步骤之后，施加比第二力高的第三力以将第一接合层和第二接合层相互挤压。

7. 发明申请

US20130099355A1 MEMS Structures and Methods for Forming the Same 有权
公开(公告)号：US20130099355A1
公开(公告)日：2013-04-25
申请号：US13280075
申请日：2011-10-24
申请人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
发明人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： B81B7/0058 , B81B3/0005 , B81B3/0021 , B81C1/00269 , B81C1/00793 , B81C2201/053 , B81C2203/0109 , H01G5/16 , H01L28/60
摘要： A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer

8. 发明授权

US08343789B2 Microstructure device with an improved anchor 有权
标题翻译：具有改进锚的微结构装置
公开(公告)号：US08343789B2
公开(公告)日：2013-01-01
申请号：US12858202
申请日：2010-08-17
申请人： Chung-Hsien Lin , Chun-Wen Cheng , Chia-Hua Chu , Yi Heng Tsai
发明人： Chung-Hsien Lin , Chun-Wen Cheng , Chia-Hua Chu , Yi Heng Tsai
IPC分类号： H01L21/02
CPC分类号： H01L29/84 , B81B2203/0109 , B81B2203/0118 , B81B2203/0307 , B81C1/00571
摘要： The present disclosure provides a system of fabricating a microstructure device with an improved anchor. A method of fabricating a microstructure device with an improved anchor includes providing a substrate and forming an oxide layer on the substrate. Then, a cavity is etched in the oxide layer, such that the cavity includes a sidewall in the oxide layer. A microstructure device layer is then bonded to the oxide layer over the cavity. Forming a microstructure device, a trench is etched in the device layer to define an outer boundary of the microstructure device. In an embodiment, the outer boundary is substantially outside of the sidewall of the cavity. Then, the sidewall of the cavity is etched away through the trench in the device layer, to thereby suspend the microstructure device over the cavity.
摘要翻译：本公开提供了一种制造具有改进的锚的微结构装置的系统。利用改进的锚固件制造微结构器件的方法包括提供衬底并在衬底上形成氧化物层。然后，在氧化物层中蚀刻空腔，使得空腔包括在氧化物层中的侧壁。然后将微结构器件层与空腔上的氧化物层结合。形成微结构器件，在器件层中蚀刻沟槽以限定微结构器件的外边界。在一个实施例中，外部边界基本上在空腔的侧壁的外侧。然后，通过器件层中的沟槽蚀刻空腔的侧壁，从而将微结构器件悬浮在空腔上。

9. 发明授权

US08330559B2 Wafer level packaging 有权
标题翻译：晶圆级包装
公开(公告)号：US08330559B2
公开(公告)日：2012-12-11
申请号：US12879216
申请日：2010-09-10
申请人： Chun-Wen Cheng , Chung-Hsien Lin , Chia-Hua Chu
发明人： Chun-Wen Cheng , Chung-Hsien Lin , Chia-Hua Chu
IPC分类号： H03H9/00
CPC分类号： B81B7/0032 , B81C1/00269 , B81C1/00333
摘要： A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
摘要翻译：晶片级封装的方法包括提供包括掩埋氧化物层和顶部氧化物层的衬底，以及蚀刻衬底以在掩埋氧化物层之上形成开口和在开口之间的微电子机械系统（MEMS）谐振器元件，封装在掩埋氧化物层内的MEMS谐振器元件，顶部氧化物层和侧壁氧化物层。该方法还包括用多晶硅填充开口以形成邻近MEMS谐振器元件的多晶硅电极，去除与MEMS谐振器元件相邻的顶部氧化物层和侧壁氧化物层，将多晶硅电极连接到互补金属氧化物半导体（CMOS ）晶片或载体晶片，去除邻近MEMS谐振器元件的掩埋氧化物层，以及将衬底接合到封盖晶片，以密封封装晶片和CMOS晶片或载体晶片之一中的MEMS谐振器元件。

10. 发明申请

US20120125747A1 MEMS SWITCH WITH REDUCED DIELECTRIC CHARGING EFFECT 有权
标题翻译：具有降低电介质充电效应的MEMS开关
公开(公告)号：US20120125747A1
公开(公告)日：2012-05-24
申请号：US12951492
申请日：2010-11-22
申请人： Chia-Hua Chu , Chung-Hsien Lin , Chun-Wen Cheng
发明人： Chia-Hua Chu , Chung-Hsien Lin , Chun-Wen Cheng
IPC分类号： H01H57/00 , H01H11/00
CPC分类号： H01H11/00 , H01G5/18 , H01H49/00 , H01H59/0009 , H01H2001/0084 , H01P1/127 , Y10T29/49105
摘要： The present disclosure provides in one embodiment, a semiconductor device that includes a MEMS switch having a substrate, a first dielectric layer disposed above the substrate, and a bottom signal electrode, a bump, and a bottom actuation electrode disposed above the first dielectric layer. The MEMS switch further includes a second dielectric layer enclosing the bottom signal electrode, and a movable member including a top signal electrode disposed above the bottom signal electrode and a top actuation electrode disposed above the bottom actuation electrode and the bump, wherein the top actuation electrode is electrically coupled to the bump. A method of fabricating a MEMS switch is also disclosed.
摘要翻译：本公开在一个实施例中提供了一种半导体器件，其包括具有衬底的MEMS开关，设置在衬底上方的第一电介质层，以及设置在第一电介质层上方的底部信号电极，凸块和底部致动电极。 MEMS开关还包括封装底部信号电极的第二电介质层和包括设置在底部信号电极上方的顶部信号电极的可移动部件和设置在底部致动电极和凸起上方的顶部致动电极，其中顶部致动电极电连接到凸块。还公开了一种制造MEMS开关的方法。

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