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1. 发明授权

US08405160B2 Multi-strained source/drain structures 有权
标题翻译：多应变源/漏结构
公开(公告)号：US08405160B2
公开(公告)日：2013-03-26
申请号：US12787972
申请日：2010-05-26
申请人： Chun-Fai Cheng , Fung Ka Hing , Ming-Huan Tsai , Chun-Feng Nieh , Yimin Huang , Han-Ting Tsai , Haiting Wang
发明人： Chun-Fai Cheng , Fung Ka Hing , Ming-Huan Tsai , Chun-Feng Nieh , Yimin Huang , Han-Ting Tsai , Haiting Wang
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/26586 , H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.
摘要翻译：本发明提供一种半导体器件。半导体器件包括硅衬底。半导体器件包括设置在衬底中的第一和第二区域。第一和第二区域具有硅化合物材料。半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。半导体器件包括设置在衬底上的第一栅极。第一个门第一个靠近第一个地区。半导体器件包括设置在衬底上的第二栅极。第二个门第二个靠近第二个区域。第二接近度与第一接近度不同。第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

2. 发明申请

US20110291201A1 MULTI-STRAINED SOURCE/DRAIN STRUCTURES 有权
标题翻译：多应变源/排水结构
公开(公告)号：US20110291201A1
公开(公告)日：2011-12-01
申请号：US12787972
申请日：2010-05-26
申请人： Chun-Fai Cheng , Fung Ka Hing , Ming-Huan Tsai , Chun-Feng Nieh , Yimin Huang , Han-Ting Tsai , Haiting Wang
发明人： Chun-Fai Cheng , Fung Ka Hing , Ming-Huan Tsai , Chun-Feng Nieh , Yimin Huang , Han-Ting Tsai , Haiting Wang
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/26586 , H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.
摘要翻译：本发明提供一种半导体器件。半导体器件包括硅衬底。半导体器件包括设置在衬底中的第一和第二区域。第一和第二区域具有硅化合物材料。半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。半导体器件包括设置在衬底上的第一栅极。第一个门第一个靠近第一个地区。半导体器件包括设置在衬底上的第二栅极。第二个门第二个靠近第二个区域。第二接近度不同于第一接近度。第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

3. 发明授权

US08569139B2 Method of manufacturing strained source/drain structures 有权
公开(公告)号：US08569139B2
公开(公告)日：2013-10-29
申请号：US12913041
申请日：2010-10-27
申请人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
发明人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
IPC分类号： H01L21/336 , H01L21/461
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66492 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

4. 发明申请

US20120091539A1 FACET-FREE SEMICONDUCTOR DEVICE 有权
标题翻译：无分子半导体器件
公开(公告)号：US20120091539A1
公开(公告)日：2012-04-19
申请号：US12905579
申请日：2010-10-15
申请人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
发明人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/165 , H01L21/28123 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.
摘要翻译：描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。有源区域具有与隔离区域相接合的第一边缘。形成在半导体衬底上的栅极结构。间隔元件邻接栅极结构并覆盖在第一边缘上。在一个实施例中，隔离区域是STI结构。可以在间隔物附近形成外延区域。在实施例中，该外延区域是无面的。

5. 发明授权

US08680625B2 Facet-free semiconductor device 有权
标题翻译：无方块半导体器件
公开(公告)号：US08680625B2
公开(公告)日：2014-03-25
申请号：US12905579
申请日：2010-10-15
申请人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
发明人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
IPC分类号： H01L27/088
CPC分类号： H01L29/165 , H01L21/28123 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.
摘要翻译：描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。有源区域具有与隔离区域相接合的第一边缘。形成在半导体衬底上的栅极结构。间隔元件邻接栅极结构并覆盖在第一边缘上。在一个实施例中，隔离区域是STI结构。可以在间隔物附近形成外延区域。在实施例中，该外延区域是无面的。

6. 发明授权

US09595477B2 Semiconductor device including an epitaxy region 有权
标题翻译：包括外延区域的半导体器件
公开(公告)号：US09595477B2
公开(公告)日：2017-03-14
申请号：US13010028
申请日：2011-01-20
申请人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
发明人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
IPC分类号： H01L21/4763 , H01L21/8238 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/04 , H01L29/0649 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.
摘要翻译：描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。第一间隔物的实例组成是SiCN。

7. 发明申请

US20120187459A1 SEMICONDUCTOR DEVICE INCLUDING AN EPITAXY REGION 有权
标题翻译：包括外延地区的半导体器件
公开(公告)号：US20120187459A1
公开(公告)日：2012-07-26
申请号：US13010028
申请日：2011-01-20
申请人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
发明人： Te-Jen Pan , Yu-Hsien Lin , Hsiang-Ku Shen , Wei-Han Fan , Yun Jing Lin , Yimin Huang , Tzu-Chung Wang
IPC分类号： H01L29/772 , H01L21/28 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/04 , H01L29/0649 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.
摘要翻译：描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。第一间隔物的实例组成是SiCN。

8. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

9. 发明授权

US06680248B2 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06680248B2
公开(公告)日：2004-01-20
申请号：US09991131
申请日：2001-11-20
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.
摘要翻译：形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。沟槽和第一开口一起形成双镶嵌结构的开口。最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

10. 发明授权

US06388326B2 Bonding pad on a semiconductor chip 失效
标题翻译：接合焊盘在半导体芯片上
公开(公告)号：US06388326B2
公开(公告)日：2002-05-14
申请号：US09800574
申请日：2001-03-08
申请人： Hermen Liu , Yimin Huang
发明人： Hermen Liu , Yimin Huang
IPC分类号： H01L2328
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/48463 , H01L2924/0001 , H01L2924/01009 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/00015 , H01L2924/00014 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.
摘要翻译：本发明提供了半导体芯片上的接合焊盘，从而避免了在封装过程中的互连期间剥离焊盘。焊盘用于将半导体芯片中的集成电路与外部电路电连接。半导体芯片包括位于半导体芯片的表面上的预定区域中的第一电介质层，位于半导体芯片的表面上的第二电介质层，其中第一电介质层比第二介电层硬，以及位于第一电介质层上的用于将半导体芯片中的集成电路（IC）电连接到外部电路的接合焊盘。

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