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1. 发明授权

US06388326B2 Bonding pad on a semiconductor chip 失效
标题翻译：接合焊盘在半导体芯片上
公开(公告)号：US06388326B2
公开(公告)日：2002-05-14
申请号：US09800574
申请日：2001-03-08
申请人： Hermen Liu , Yimin Huang
发明人： Hermen Liu , Yimin Huang
IPC分类号： H01L2328
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/48463 , H01L2924/0001 , H01L2924/01009 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/00015 , H01L2924/00014 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.
摘要翻译：本发明提供了半导体芯片上的接合焊盘，从而避免了在封装过程中的互连期间剥离焊盘。焊盘用于将半导体芯片中的集成电路与外部电路电连接。半导体芯片包括位于半导体芯片的表面上的预定区域中的第一电介质层，位于半导体芯片的表面上的第二电介质层，其中第一电介质层比第二介电层硬，以及位于第一电介质层上的用于将半导体芯片中的集成电路（IC）电连接到外部电路的接合焊盘。

2. 发明授权

US06297561B1 Semiconductor chip 有权
标题翻译：半导体芯片
公开(公告)号：US06297561B1
公开(公告)日：2001-10-02
申请号：US09630529
申请日：2000-08-01
申请人： Hermen Liu , Yimin Huang
发明人： Hermen Liu , Yimin Huang
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/3171 , H01L24/10 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05553 , H01L2224/05554 , H01L2224/05557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/13 , H01L2224/13099 , H01L2224/451 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/04941 , H01L2924/05042 , H01L2924/12044 , H01L2924/14 , H01L2224/45099 , H01L2924/00015 , H01L2924/00
摘要： The present invention provides a semiconductor chip. The semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method comprises using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer comprises an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.
摘要翻译：本发明提供一种半导体芯片。包括位于半导体芯片内的集成电路（IC）的半导体芯片和位于半导体芯片的表面上且与IC电连接的接合焊盘。该方法包括使用探针接触焊盘表面上的预定测试区域以对IC进行电测试，以及在半导体芯片的表面上形成钝化层以钝化半导体芯片的表面。接合焊盘的测试区域被覆盖在钝化层下方，并且钝化层包括位于测试区域外的焊盘上的开口，该开口用作用于进行引线接合或凸起的连接区域。

3. 发明授权

US06372621B1 Method of forming a bonding pad on a semiconductor chip 失效
标题翻译：在半导体芯片上形成接合焊盘的方法
公开(公告)号：US06372621B1
公开(公告)日：2002-04-16
申请号：US09293963
申请日：1999-04-19
申请人： Hermen Liu , Yimin Huang
发明人： Hermen Liu , Yimin Huang
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/48463 , H01L2924/0001 , H01L2924/01009 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/00015 , H01L2924/00014 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： The present invention provides a method of forming a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The method comprises forming a first dielectric layer at a predetermined area on the surface of the semiconductor chip, forming a second dielectric layer on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and forming the bonding pad on the first dielectric layer.
摘要翻译：本发明提供了一种在半导体芯片上形成接合焊盘的方法，从而避免了在封装过程中的互连期间剥离焊盘。焊盘用于将半导体芯片中的集成电路与外部电路电连接。该方法包括在半导体芯片的表面上的预定区域形成第一电介质层，在第一电介质层比第二电介质层硬的预定区域外的半导体芯片的表面上形成第二电介质层，以及在第一电介质层上形成接合焊盘。

4. 发明授权

US06251694B1 Method of testing and packaging a semiconductor chip 有权
标题翻译：测试和封装半导体芯片的方法
公开(公告)号：US06251694B1
公开(公告)日：2001-06-26
申请号：US09318597
申请日：1999-05-26
申请人： Hermen Liu , Yimin Huang
发明人： Hermen Liu , Yimin Huang
IPC分类号： H01L3126
CPC分类号： H01L22/20 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05124 , H01L2224/05166 , H01L2224/05553 , H01L2224/05557 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099 , H01L2924/00015 , H01L2924/00
摘要： The present invention provides a method of testing and packaging a semiconductor chip. The semiconductor chip includes an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method includes using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer has an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.
摘要翻译：本发明提供一种测试和封装半导体芯片的方法。半导体芯片包括位于半导体芯片内的集成电路（IC）和位于半导体芯片的表面上且与IC电连接的接合焊盘。该方法包括使用探针接触焊盘表面上的预定测试区域以对IC进行电测试，以及在半导体芯片的表面上形成钝化层以钝化半导体芯片的表面。接合焊盘的测试区域被覆盖在钝化层下方，并且钝化层具有位于测试区域外部的焊盘上的开口，该开口用作用于进行引线接合或凸起的连接区域。

5. 发明申请

US20120091539A1 FACET-FREE SEMICONDUCTOR DEVICE 有权
标题翻译：无分子半导体器件
公开(公告)号：US20120091539A1
公开(公告)日：2012-04-19
申请号：US12905579
申请日：2010-10-15
申请人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
发明人： Wei-Han Fan , Yu-Hsien Lin , Yimin Huang , Ming-Huan Tsai , Hsueh-Chang Sung , Chun-Fai Cheng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/165 , H01L21/28123 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.
摘要翻译：描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。有源区域具有与隔离区域相接合的第一边缘。形成在半导体衬底上的栅极结构。间隔元件邻接栅极结构并覆盖在第一边缘上。在一个实施例中，隔离区域是STI结构。可以在间隔物附近形成外延区域。在实施例中，该外延区域是无面的。

6. 发明授权

US06987057B2 Method making bonding pad 有权
标题翻译：方法制作焊盘
公开(公告)号：US06987057B2
公开(公告)日：2006-01-17
申请号：US10229443
申请日：2002-08-27
申请人： Ellis Lee , Yimin Huang , Tri-Rung Yew
发明人： Ellis Lee , Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
摘要翻译：焊盘结构在铜层上具有钝化层，该钝化层具有用于暴露铜层的一部分的焊盘窗口，与焊盘窗口的轮廓一致的阻挡层和位于焊盘窗口中的铝焊盘。金属层可以是铝，铝合金或铝主导层，用于在铜层和接合线之间提供更好的粘合性能。

7. 发明授权

US06593223B1 Method of forming dual damascene structure 有权
公开(公告)号：US06593223B1
公开(公告)日：2003-07-15
申请号：US09524720
申请日：2000-03-14
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

8. 发明授权

US06211068B1 Dual damascene process for manufacturing interconnects 有权
标题翻译：用于制造互连的双镶嵌工艺
公开(公告)号：US06211068B1
公开(公告)日：2001-04-03
申请号：US09318228
申请日：1999-05-25
申请人： Yimin Huang
发明人： Yimin Huang
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76804
摘要： A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that expose a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned, and the photoresist material inside the opening is turned into a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening. Metal is finally deposited into the opening and the trenches to complete the dual damascene process.
摘要翻译：用于生产互连的双镶嵌工艺。双镶嵌工艺包括在其上具有导电层的衬底上形成蚀刻停止层，并在蚀刻停止层上形成层间电介质层。在电介质层上形成掩模层。掩模层和层间电介质层被图案化以形成露出蚀刻停止层的一部分的开口。开口形成在导电层的上方。光刻胶材料沉积在掩模层上并进入开口。光致抗蚀剂层和掩模层被图案化，并且开口内部的光致抗蚀剂材料同时变成光致抗蚀剂插塞。去除光致抗蚀剂插塞的顶层。使用图案化的光致抗蚀剂层和掩模层作为掩模，进行各向异性蚀刻步骤以在层间电介质层内部形成多个沟槽。这些沟槽与开口重叠。金属最终沉积到开口和沟槽中以完成双镶嵌工艺。

9. 发明授权

US6159661A Dual damascene process 失效
标题翻译：双镶嵌工艺
公开(公告)号：US6159661A
公开(公告)日：2000-12-12
申请号：US73997
申请日：1998-05-07
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/314 , H01L21/768 , G03F7/00
CPC分类号： H01L21/76832 , H01L21/3143 , H01L21/7681
摘要： An improved dual damascene process for forming metal interconnects comprising the steps of providing a semiconductor substrate that has a conductive layer, a first dielectric layer and a first mask layer already formed thereon. The first dielectric layer is made from a low-k dielectric material. A first silicon oxynitride (SiON) layer is formed over the first mask layer. Next, the first silicon oxynitride layer is patterned, and then the first mask layer is etched using the first silicon oxynitride as a mask. Subsequently, a second dielectric layer and a second mask layer are formed over the first silicon oxynitride. The second dielectric layer can be made from a low-k dielectric material. Next, a second silicon oxynitride layer is formed over the second mask layer. Thereafter, the second silicon oxynitride layer is patterned, and then the second mask layer is etched using the second silicon oxynitride layer as a mask. Subsequently, using the second mask layer as a mask, the second dielectric layer is etched to form a metal wire opening. Etching continues down the metal wire opening to form a via opening in the first dielectric layer that exposes the conductive layer. Finally, metal is deposited into the metal wire opening and the via opening to form the dual damascene structure of this invention.
摘要翻译：一种用于形成金属互连的改进的双镶嵌工艺，包括以下步骤：提供具有导电层，第一介电层和已形成在其上的第一掩模层的半导体衬底。第一电介质层由低k电介质材料制成。在第一掩模层上形成第一氮氧化硅（SiON）层。接下来，对第一氮氧化硅层进行构图，然后使用第一氧氮化硅作为掩模蚀刻第一掩模层。随后，在第一氮氧化硅上形成第二电介质层和第二掩模层。第二电介质层可以由低k电介质材料制成。接下来，在第二掩模层上形成第二氧氮化硅层。此后，对第二氮氧化硅层进行构图，然后使用第二氮氧化硅层作为掩模蚀刻第二掩模层。随后，使用第二掩模层作为掩模，蚀刻第二介电层以形成金属丝开口。蚀刻在金属线开口处继续向下以在暴露导电层的第一介电层中形成通孔。最后，将金属沉积到金属丝开口和通孔中以形成本发明的双镶嵌结构。

10. 发明授权

US6084304A Structure of metallization 失效
标题翻译：金属化结构
公开(公告)号：US6084304A
公开(公告)日：2000-07-04
申请号：US100769
申请日：1998-06-05
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L23/485
CPC分类号： H01L23/53228 , H01L2224/85375
摘要： A metallization structure comprises a semiconductor substrate and pre-formed multi-interconnect layer, which include a passivation layer deposited on the top copper layer of the multi-interconnect layer, a pad window, and a non-copper thin conductive film. The non-copper thin conductive film is deposited in the pad window to protect the top copper layer from exposure to the air. The non-copper thin conductive film includes aluminum, tantalum, TaN, TiN, or WN.
摘要翻译：金属化结构包括半导体衬底和预成形的多互连层，其包括沉积在多互连层的顶部铜层上的钝化层，焊盘窗口和非铜薄导电膜。非铜薄导电膜沉积在焊盘窗口中以保护顶部铜层不暴露于空气中。非铜薄导电膜包括铝，钽，TaN，TiN或WN。

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