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1. 发明授权

US5411907A Capping free metal silicide integrated process 失效
标题翻译：无盖金属硅化物集成工艺
公开(公告)号：US5411907A
公开(公告)日：1995-05-02
申请号：US937735
申请日：1992-09-01
申请人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
发明人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/6659
摘要： A method is described for fabricating a lightly doped drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode continues by annealing the gate oxide, the polysilicon layer and the metal silicide layer using a furnace process at a temperature more than about 920.degree. C. and for a time of less than about 40 minutes. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The pattern of lightly doped regions is driven in while maintaining the low temperature silicon oxide over the metal silicide layer by annealing at a temperature of more than about 920.degree. C. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Heavily doped regions are formed. A passivation layer which includes a silicon oxide layer and a thicker dielectric layer is formed over the structures. The heavily doped regions are annealed to drivein the impurities at a temperature of more than about 920.degree. C. while maintaining said passivation layer over said metal silicide layer.
摘要翻译：描述了一种用于制造具有无剥离金属硅化物栅电极的轻掺杂漏极MOS FET集成电路器件的方法，其通过使用炉法在大于约920的温度下退火栅极氧化物，多晶硅层和金属硅化物层并且时间小于约40分钟。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。驱动轻掺杂区域的图案，同时通过在超过约920℃的温度下退火，在金属硅化物层上保持低温氧化硅的同时，蚀刻覆盖层以在每个侧壁上形成电介质间隔物结构的栅极电极结构和衬底的相邻部分之上，并从金属硅化物层的顶表面去除氧化硅层。形成重掺杂区域。在结构上形成包括氧化硅层和较厚电介质层的钝化层。重掺杂区域被退火以在大于约920℃的温度下驱动杂质，同时将所述钝化层保持在所述金属硅化物层上。

2. 发明授权

US5837578A Process of manufacturing a trenched stack-capacitor 失效
标题翻译：制造沟槽叠层电容器的工艺
公开(公告)号：US5837578A
公开(公告)日：1998-11-17
申请号：US895107
申请日：1997-07-16
申请人： Der-Tsyr Fan , Jyh-Min Tsaur , Chon-Shin Jou , Tings Wang
发明人： Der-Tsyr Fan , Jyh-Min Tsaur , Chon-Shin Jou , Tings Wang
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density. The process includes steps of: a) forming a contact window in the insulator for exposing a cell contact of the device; b) forming a first conducting layer over the insulator and on side-walls and a base of the contact window; c) forming an etching sacrificial layer over the first conducting layer and in the contact window; d) forming an etching masking layer over a portion of the etching sacrificial layer; e) forming a plural cylindrical etching sacrificial areas by removing an another portion of the etching sacrificial layer while retaining the etching sacrificial layer under the etching masking layer; f) forming a second conducting layer on the top of the etching masking layer, on side walls of the plural cylindrical etching sacrificial areas, over the first conducting layer and in the contact window; g) removing the plural cylindrical etching sacrificial areas while retaining the first conducting layer and the second conducting layer to form a first capacitor plate; h) forming a dielectric layer on the top of the first conducting layer and on the top and side walls of the second conducting layer; and i) forming a third conducting layer over the dielectric layer to serve as a second capacitor plate.
摘要翻译：施加在存储器单元中的沟槽叠层电容器通过制造高密度堆叠电容器的简单工艺形成。该方法包括以下步骤：a）在绝缘体中形成接触窗口，用于暴露设备的电池接触; b）在所述绝缘体上以及所述接触窗的侧壁和底座上形成第一导电层; c）在所述第一导电层上和所述接触窗中形成蚀刻牺牲层; d）在蚀刻牺牲层的一部分上形成蚀刻掩模层; e）通过去除蚀刻牺牲层的另一部分同时将蚀刻牺牲层保持在蚀刻掩模层下方而形成多个圆柱形蚀刻牺牲区域; f）在所述蚀刻掩模层的顶部，在所述多个圆柱形蚀刻牺牲区域的侧壁上，在所述第一导电层和所述接触窗口之上形成第二导电层; g）在保留第一导电层和第二导电层以形成第一电容器板的同时，去除多个圆柱形蚀刻牺牲区域; h）在第一导电层的顶部和第二导电层的顶壁和侧壁上形成电介质层; 以及i）在所述电介质层上形成第三导电层以用作第二电容器板。

3. 发明授权

US5480828A Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process 失效
标题翻译：通过抑制或提高混合3/5 V CMOS工艺的氧化速率的差分栅极氧化工艺
公开(公告)号：US5480828A
公开(公告)日：1996-01-02
申请号：US316084
申请日：1994-09-30
申请人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
发明人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S148/116 , Y10S438/981
摘要： A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.
摘要翻译：描述了同时形成3和5 V晶体管的差分栅极氧化物的新方法。牺牲氧化硅层形成在半导体衬底的表面上。离子通过牺牲氧化硅层注入到半导体衬底的预定的3V晶体管区域中，其中注入的离子降低半导体衬底的氧化速率。或者，离子通过牺牲氧化硅层注入到半导体衬底的预定的5V晶体管区域中，其中注入的离子增加了半导体衬底的氧化速率。去除牺牲氧化硅层，并在半导体衬底的表面上生长栅极氧化硅层。栅极氧化硅的生长速率将在预定的3 V晶体管面积中减慢，或者将在计划的5 V晶体管区域中增加，从而导致栅极氧化硅层在计划的3 V晶体管区域中相对较薄，并且相对较厚在计划的5 V晶体管区域。一层多晶硅沉积在栅极氧化硅层上并被图案化以形成用于3V和5V晶体管的栅电极。

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