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1. 发明授权

US5480828A Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process 失效
标题翻译：通过抑制或提高混合3/5 V CMOS工艺的氧化速率的差分栅极氧化工艺
公开(公告)号：US5480828A
公开(公告)日：1996-01-02
申请号：US316084
申请日：1994-09-30
申请人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
发明人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S148/116 , Y10S438/981
摘要： A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.
摘要翻译：描述了同时形成3和5 V晶体管的差分栅极氧化物的新方法。牺牲氧化硅层形成在半导体衬底的表面上。离子通过牺牲氧化硅层注入到半导体衬底的预定的3V晶体管区域中，其中注入的离子降低半导体衬底的氧化速率。或者，离子通过牺牲氧化硅层注入到半导体衬底的预定的5V晶体管区域中，其中注入的离子增加了半导体衬底的氧化速率。去除牺牲氧化硅层，并在半导体衬底的表面上生长栅极氧化硅层。栅极氧化硅的生长速率将在预定的3 V晶体管面积中减慢，或者将在计划的5 V晶体管区域中增加，从而导致栅极氧化硅层在计划的3 V晶体管区域中相对较薄，并且相对较厚在计划的5 V晶体管区域。一层多晶硅沉积在栅极氧化硅层上并被图案化以形成用于3V和5V晶体管的栅电极。

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