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1. 发明授权

US6061785A Data processing system having an apparatus for out-of-order register operations and method therefor 失效
标题翻译：数据处理系统具有无序寄存器操作的装置及其方法
公开(公告)号：US6061785A
公开(公告)日：2000-05-09
申请号：US24804
申请日：1998-02-17
申请人： Kevin Arthur Chiarot , A. James Van Norstrand, Jr. , David Andrew Schroter
发明人： Kevin Arthur Chiarot , A. James Van Norstrand, Jr. , David Andrew Schroter
IPC分类号： G06F9/305 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.
摘要翻译：实现了条件寄存器（CR）重命名的装置及其使用方法。在具有流水线架构的中央处理单元（CPU）中，使用CR重命名机制可以执行对无效操作数的逻辑运算。更新CR数据的任何指令都具有存储在寄存器中的关联指令标识符（IID）。使用CR中的数据的后续条件寄存器逻辑（LCR）指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新CR数据。当导致CR数据值更新的指令完成执行时，通过窥探相应执行单元的完成总线来获得更新的数据。以这种方式，这些指令可以在完成前面的指令之前获得CR数据。因为在更新指令完成之前更新的CR数据可用于下一个执行的LCR，从而实现了反序列化执行LCR指令。

2. 发明授权

US6035394A System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel 失效
标题翻译：用于通过在并行装载/存储单元和定序器中产生原始指令来提供复杂加载/存储指令的高性能推测性处理的系统
公开(公告)号：US6035394A
公开(公告)日：2000-03-07
申请号：US24805
申请日：1998-02-17
申请人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
发明人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.
摘要翻译：本发明的一个方面涉及一种用于操作具有指令高速缓存，排序单元，加载/存储单元，高速缓存，架构寄存器文件和重命名寄存器文件的超标量处理器的方法。在本发明的一个特定版本中，该方法包括以下步骤：将指令从指令高速缓存转发到可操作以访问多个架构寄存器的排序单元; 响应于转发的指令产生多个原语指令，其中单个原语指令可操作以访问单个体系结构寄存器; 并顺序地发出原始指令以在数据高速缓存和重命名寄存器文件之间移动数据。

3. 发明授权

US5634119A Computer processing unit employing a separate millicode branch history table 失效
标题翻译：计算机处理单元采用单独的millicode分支历史表
公开(公告)号：US5634119A
公开(公告)日：1997-05-27
申请号：US369441
申请日：1995-01-06
申请人： Philip G. Emma , Joshua W. Knight, III , Thomas R. Puzak , James R. Robinson , A. James Van Norstrand, Jr.
发明人： Philip G. Emma , Joshua W. Knight, III , Thomas R. Puzak , James R. Robinson , A. James Van Norstrand, Jr.
IPC分类号： G06F9/318 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table.The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.
摘要翻译：计算机处理系统包括存储属于第一指令集架构的指令的第一存储器和存储属于第二指令集架构的指令的第二存储器。指令缓冲器耦合到第一和第二存储器，用于存储由处理器单元执行的指令。该系统以两种模式之一运行。在第一模式中，根据存储在第一分支历史表中的数据，将指令从第一存储器提取到指令缓冲器中。在第二模式中，根据存储在第二分支历史表中的数据，将指令从第二存储器提取到指令缓冲器中。第一指令集架构可以是系统级指令，并且第二指令集架构可以是例如定义复杂系统级指令和/或模拟第三指令集体系结构的毫指令指令。

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