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1. 发明授权

US5408674A System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size 失效
标题翻译：用于通过将两个字节的操作码映射到控制存储器中以检查两字节操作码的有效性的系统，以减少存储器大小
公开(公告)号：US5408674A
公开(公告)日：1995-04-18
申请号：US995772
申请日：1992-12-23
申请人： Christopher I. W. Norrie , Carolee N. Newcomb , Peter K. Yu
发明人： Christopher I. W. Norrie , Carolee N. Newcomb , Peter K. Yu
IPC分类号： G06F9/30 , G06F9/32 , G06F9/28
CPC分类号： G06F9/30145
摘要： A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies that specific operation code within the identified series, the mapping system comprising a first register for storing the first and second bytes of a two byte operation codes, a first control store for storing control word for the two byte operation codes, a first means for generating, from the first and second bytes stored in the first register, a first control store address for the first control store thereby providing access to the control word for processing the two byte operation code store in the first register and a second means for generating, from the first and second bytes stored in the first register, a first signal when an invalid two byte operation code has been stored in the first register for processing, the first signal invalidating the processing of the two byte operation code stored in the first register including any processing of the control word accessed by the first control store in response to the first control store address generated by the first means.
摘要翻译：一种用于将多个两字节操作代码序列映射到控制存储器中的映射系统，其中在每个两字节操作代码中，第一字节标识包含该两字节操作代码的序列，而第二字节标识该字节内的特定操作码所述映射系统包括用于存储两字节操作码的第一和第二字节的第一寄存器，用于存储用于所述两字节操作码的控制字的第一控制存储器，用于从所述第一和第二字节存储在第一寄存器中的字节，用于第一控制存储器的第一控制存储地址，从而提供对用于处理第一寄存器中的两字节操作代码存储的控制字的访问;以及第二装置，用于从存储的第一和第二字节在第一个寄存器中，第一个信号当一个无效的两个字节的操作码已被存储在第一个寄存器中进行处理时，第一个信号进入验证存储在第一寄存器中的两字节操作码的处理，包括响应于由第一装置产生的第一控制存储地址由第一控制存储器访问的控制字的任何处理。

2. 发明授权

US5386549A Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture 失效
标题翻译：用于恢复在采用管道架构的计算机系统中的控制存储中发生的错误的错误恢复系统
公开(公告)号：US5386549A
公开(公告)日：1995-01-31
申请号：US978829
申请日：1992-11-19
申请人： Christopher I. W. Norrie , Carolee V. Newcomb , Peter K. Yu , Allan Zmyslowski
发明人： Christopher I. W. Norrie , Carolee V. Newcomb , Peter K. Yu , Allan Zmyslowski
IPC分类号： G06F11/00 , G06F11/10 , H03M13/00
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1076 , G06F11/1405
摘要： An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing control words by the computer system. The computer system processes instructions in a sequence of overlapping FLOWs where each FLOW is comprised of a sequence of cycles. An instruction control word is processed in each cycle of each FLOW. The error recovery system comprises a first storage for storing, for a given cycle of a FLOW, all the control words for all the instructions, a second storage for storing a control word read from the first storage and an error recovery logic for detecting an error in the control word read from the first storage and stored in the second storage and for correcting the error in the control word in the first and second storage.
摘要翻译：一种在流水线架构型计算机系统中使用的错误恢复系统，用于从指令的控制字中的错误中恢复，而不会中断计算机系统处理控制字的序列。计算机系统处理重叠FLOW序列中的指令，其中每个FLOW由循环序列组成。在每个流程的每个循环中处理指令控制字。错误恢复系统包括第一存储器，用于在FLOW的给定周期中存储用于所有指令的所有控制字，用于存储从第一存储器读取的控制字的第二存储器和用于检测错误的错误恢复逻辑在从第一存储器读取并存储在第二存储器中的控制字中，并用于校正第一和第二存储器中的控制字中的错误。

3. 发明授权

US06748567B1 Method and system for error correction over serial link 有权
标题翻译：通过串行链路进行纠错的方法和系统
公开(公告)号：US06748567B1
公开(公告)日：2004-06-08
申请号：US09846875
申请日：2001-05-01
申请人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
发明人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
IPC分类号： H03M1305
CPC分类号： H03M13/098 , H03M13/09
摘要： A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data that is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verify the integrity of the transmitted ECC code itself.
摘要翻译：根据本发明的系统和方法产生在y位域中发送的ECC码，以及从本机x位域转换到y位域的数据。这样的系统和方法提供作为允许时钟恢复并且可以使用奇偶校验或其他方法来验证所发送的ECC代码本身的完整性的传输串行流的一部分的ECC代码的表示。

4. 发明授权

US5490255A Expedited execution of pipelined command having self-ordering operand processing requirements 失效
标题翻译：快速执行具有自订操作数处理要求的流水线命令
公开(公告)号：US5490255A
公开(公告)日：1996-02-06
申请号：US814878
申请日：1991-12-26
申请人： Stephen J. Rawlinson , Christopher I. W. Norrie
发明人： Stephen J. Rawlinson , Christopher I. W. Norrie
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30025 , G06F9/3824 , G06F9/383 , G06F9/3867
摘要： A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stage at a later time. The sidetracking mechanism is used to speed processing of rate-variable operand-consuming instructions such as the EDIT and EDMK commands.
摘要翻译：通过D，A，T，B，X和W级序列处理操作数数据的流水线计算机包括一个侧向队列。在X阶段准备好立即处理这样的数据之前提前退出B阶段的数据被保持在侧面队列中，并在稍后的时间被呈现给X阶段。旁路机制用于加速诸如EDIT和EDMK命令之类的速率变量操作使用指令的处理。

5. 发明授权

US07647438B1 Binary base address sorting method and device with shift vector 有权
标题翻译：二进制基地址排序方法和具有移位向量的设备
公开(公告)号：US07647438B1
公开(公告)日：2010-01-12
申请号：US11382480
申请日：2006-05-09
申请人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
发明人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
IPC分类号： G06F19/00 , G06F12/02
CPC分类号： G06F7/24
摘要： A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.
摘要翻译：公开了一种开关装置中的基地址分类装置，其包括基地址寄存器阵列，其中每个基地址寄存器包含基地址，地址移位装置; 以及控制逻辑元件，其电耦合到所述基地址寄存器阵列，并且在接收到包括新的基地址的配置命令时可操作以实现用于重新配置所述基地址寄存器阵列的内容的方法。该方法包括确定写入新基址的基地址寄存器阵列中的插入点基地址寄存器，将一个或多个基地址寄存器阵列的内容移位到其他基地址寄存器以保持排序顺序，将配置命令的内容插入到插入点基地址寄存器中。插入导致保留寄存器阵列内容的预定顺序。

6. 发明授权

US07454554B1 Binary base address search device and method 失效
标题翻译：二进制基地址搜索设备和方法
公开(公告)号：US07454554B1
公开(公告)日：2008-11-18
申请号：US11395715
申请日：2006-03-31
申请人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
发明人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
IPC分类号： G06F13/00 , H04L12/56 , G06F13/14
CPC分类号： H04L49/3009 , H04L49/35
摘要： A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.
摘要翻译：公开了一种基地址匹配装置和方法。在具有多个输入/输出端口的开关设备中，已经描述了具有寄存器阵列的路由设备，其中每个寄存器保持将地址与交换设备中的输入/输出端口之一相关联的内容，以及寄存器阵列中的内容被预先排列成指定的顺序，以及地址匹配元件，其具有电耦合到寄存器阵列中的选定寄存器的多个比较器。基地址匹配元件能够从寄存器阵列的内容中选择匹配的地址，并且通过将分组中的目标地址与数据包中的目标地址匹配来将通信分组引导到交换机的一个端口中注册在与端口相关联的寄存器阵列中。

7. 发明授权

US07356722B2 Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits 有权
标题翻译：在独立时钟的源，中间和目的地电路之间可变地延迟分组的传输，同时在中间和目的电路中的一个或两个中保持有序和及时的处理
公开(公告)号：US07356722B2
公开(公告)日：2008-04-08
申请号：US11699737
申请日：2007-01-29
申请人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
IPC分类号： G06F1/12
CPC分类号： G06F1/14 , H04L2012/5674
摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.
摘要翻译：在具有独立时钟的作业执行电路（例如，有效载荷处理器）和独立时钟的作业排序电路（例如，请求和有效载荷供应商）的系统中，提供协调机制以协调独立时钟的电路之间的交换。协调机制包括使用传输的时间戳来调度所请求作业的作业执行电路内的无竞争性能的那些机制。协调机构附加地或备选地包括静态和动态速率限制装置，其被配置为防止更快时钟的一个独立时钟的电路压倒更独立时钟的电路中更慢时钟的其他电路。在一个实现中，独立时钟的电信货架容纳一组分布式的线卡和交换卡。在独立时钟的架之间提供异步互连，用于在分布式线路卡和分布式交换卡之间传送作业请求和有效载荷数据。多架系统是可扩展的和可靠的，因为可以根据需要将额外的或更换的线路和交换机卡插入独立时钟的架子中的一个或另一个，并且因为不需要统一的时钟树来同步互连的活动，而是独立时钟的货架。

8. 发明授权

US08621318B1 Nonvolatile memory controller with error detection for concatenated error correction codes 有权
标题翻译：具有错误检测功能的非易失性存储器控制器，用于级联纠错码
公开(公告)号：US08621318B1
公开(公告)日：2013-12-31
申请号：US13435572
申请日：2012-03-30
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.
摘要翻译：一种非易失性存储器控制器，用于通过执行硬判决内纠错码解码和使用硬判决内纠错码解码解码的数据的外纠错码解码来恢复编码数据，然后确定编码数据是否已成功解码。如果编码数据尚未成功解码，则控制器使用软判决算法和使用软判决内部误差解码的数据的外部纠错码解码来对编码数据执行软判决内部纠错码解码校正码解码，然后确定编码数据是否已被成功解码。如果编码数据尚未成功解码，则控制器通过对编码数据执行RAID操作来恢复数据。

9. 发明授权

US08069392B1 Error correction code system and method 有权
标题翻译：纠错码系统和方法
公开(公告)号：US08069392B1
公开(公告)日：2011-11-29
申请号：US11873357
申请日：2007-10-16
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/19 , H03M13/033 , H03M13/6575
摘要： An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correction code generator includes logic circuits for generating check bits in the error correction code. The error detector includes logic circuits for identifying any data bits of the data unit having a bit error based on the error correction code. The logic circuits in the error correction code generator and the error detector are derived from group codes separated from each other by a hamming distance and having a same population count. The error correction code system may also include an error corrector for correcting error bits in the data unit.
摘要翻译：纠错码系统包括：纠错码发生器，用于基于数据单元产生纠错码;以及误差检测器，用于基于纠错码检测数据单元中的至少一个位错误。纠错码发生器包括用于在纠错码中产生校验位的逻辑电路。误差检测器包括用于基于纠错码识别具有位错误的数据单元的任何数据位的逻辑电路。错误校正码发生器和误差检测器中的逻辑电路是从组合码中导出的，它们由汉明距离彼此分开并且具有相同的总数。纠错码系统还可以包括用于校正数据单元中的错误位的纠错器。

10. 发明授权

US07756014B1 Device and method for handling catastrophic routing 有权
标题翻译：处理灾难性路由的设备和方法
公开(公告)号：US07756014B1
公开(公告)日：2010-07-13
申请号：US11677697
申请日：2007-02-22
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： G01R31/08
CPC分类号： H04L45/00 , H04L41/0803 , H04L45/28
摘要： A method and device for handling catastrophic switch routing errors. Upon receiving a communication packet in a packet switching device, a port in the switching device is matched with the destination address of the communication packet and a routing code is generated to direct routing of the communication packet internally to the packet switching device. The routing code is analyzed to determine whether a catastrophic routing condition exists in the routing code. If no catastrophic routing condition exists, the routing is executed. However, when there is a catastrophic routing condition, execution of the routing of the communication packet is prevented.
摘要翻译：一种用于处理灾难性开关路由错误的方法和装置。在分组交换设备中接收到通信分组时，交换设备中的端口与通信分组的目的地地址相匹配，并且生成路由代码以将通信分组的内部路由引导到分组交换设备。分析路由代码以确定路由代码中是否存在灾难性路由条件。如果没有灾难性路由条件存在，路由将被执行。然而，当存在灾难性路由条件时，阻止了通信分组的路由的执行。

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