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1. 发明授权

US07356722B2 Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits 有权
标题翻译：在独立时钟的源，中间和目的地电路之间可变地延迟分组的传输，同时在中间和目的电路中的一个或两个中保持有序和及时的处理
公开(公告)号：US07356722B2
公开(公告)日：2008-04-08
申请号：US11699737
申请日：2007-01-29
申请人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
IPC分类号： G06F1/12
CPC分类号： G06F1/14 , H04L2012/5674
摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.
摘要翻译：在具有独立时钟的作业执行电路（例如，有效载荷处理器）和独立时钟的作业排序电路（例如，请求和有效载荷供应商）的系统中，提供协调机制以协调独立时钟的电路之间的交换。协调机制包括使用传输的时间戳来调度所请求作业的作业执行电路内的无竞争性能的那些机制。协调机构附加地或备选地包括静态和动态速率限制装置，其被配置为防止更快时钟的一个独立时钟的电路压倒更独立时钟的电路中更慢时钟的其他电路。在一个实现中，独立时钟的电信货架容纳一组分布式的线卡和交换卡。在独立时钟的架之间提供异步互连，用于在分布式线路卡和分布式交换卡之间传送作业请求和有效载荷数据。多架系统是可扩展的和可靠的，因为可以根据需要将额外的或更换的线路和交换机卡插入独立时钟的架子中的一个或另一个，并且因为不需要统一的时钟树来同步互连的活动，而是独立时钟的货架。

2. 发明授权

US07181485B1 Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits 有权
公开(公告)号：US07181485B1
公开(公告)日：2007-02-20
申请号：US09997507
申请日：2001-11-26
申请人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Matthew D. Ornes , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , King-Shing (Frank) Chui
IPC分类号： G06F15/16
CPC分类号： G06F1/14 , H04L2012/5674
摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

3. 发明授权

US07079485B1 Multiservice switching system with distributed switch fabric 失效
标题翻译：具有分布式交换矩阵的多业务交换系统
公开(公告)号：US07079485B1
公开(公告)日：2006-07-18
申请号：US09847711
申请日：2001-05-01
申请人： Onchuen (Daryn) Lau , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , Matthew D. Ornes , King-Shing (Frank) Chui
发明人： Onchuen (Daryn) Lau , Chris D. Bergen , Robert J. Divivier , Gene K. Chui , Christopher I. W. Norrie , Matthew D. Ornes , King-Shing (Frank) Chui
IPC分类号： H04L12/56 , H04J14/08
CPC分类号： H04L49/45 , H04L49/201 , H04L49/3045 , H04L49/357 , H04L49/503 , H04L2012/5618
摘要： A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.
摘要翻译：数字交换系统包括：（a）包含多个真实或虚拟线路卡的线路卡层; （b）包含多个实际或虚拟交换卡的交换机卡层; 以及（c）插入在线卡层和开关卡层之间的界面层，用于提供串行化支持服务，使得线卡和开关卡中的一个或多个可以可操作地和方便地设置在第一架或第一背板其与第二搁架间隔开，或者从支撑其他线路卡和/或开关卡的第二背板间隔开。这样的布置允许在服务的线路数量和/或传输速率方面可以扩展交换系统。当有效载荷数据在线路卡层和交换结构层之间移动时，系统的灵活性部分归因于在所谓的ZCell信号的有效负载区域内承载的有效载荷数据。

4. 发明授权

US07263097B1 Programmably sliceable switch-fabric unit and methods of use 失效
标题翻译：可编程切片交换机单元和使用方法
公开(公告)号：US07263097B1
公开(公告)日：2007-08-28
申请号：US09997478
申请日：2001-11-26
申请人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui , Onchuen (Daryn) Lau
发明人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui , Onchuen (Daryn) Lau
IPC分类号： H04Q11/00
CPC分类号： H04Q3/68 , H04Q3/521 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/1305 , H04Q2213/13056 , H04Q2213/13076 , H04Q2213/1334 , H04Q2213/13341
摘要： A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N′ switch matrix is programmably made to operate as if it were a plurality of S×S′ virtual switch slices, where S
摘要翻译：公开了一种可编程切割的交换结构单元（PSSU）和使用方法。可编程地使NxN'开关矩阵作为多个SxS虚拟开关片，其中S

5. 发明授权

US07848319B2 Programmably sliceable switch-fabric unit and methods of use 有权
标题翻译：可编程切片交换机单元和使用方法
公开(公告)号：US07848319B2
公开(公告)日：2010-12-07
申请号：US11830453
申请日：2007-07-30
申请人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui , Onchuen (Daryn) Lau
发明人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui , Onchuen (Daryn) Lau
IPC分类号： H04L12/50
CPC分类号： H04Q3/68 , H04Q3/521 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/1305 , H04Q2213/13056 , H04Q2213/13076 , H04Q2213/1334 , H04Q2213/13341
摘要： A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N′ switch matrix is programmably made to operate as if it were a plurality of S×S′ virtual switch slices, where S
摘要翻译：公开了一种可编程切割的交换结构单元（PSSU）和使用方法。可编程地将N×N'开关矩阵作为多个S×S'虚拟开关片进行操作，其中S

6. 发明授权

US06748567B1 Method and system for error correction over serial link 有权
标题翻译：通过串行链路进行纠错的方法和系统
公开(公告)号：US06748567B1
公开(公告)日：2004-06-08
申请号：US09846875
申请日：2001-05-01
申请人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
发明人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
IPC分类号： H03M1305
CPC分类号： H03M13/098 , H03M13/09
摘要： A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data that is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verify the integrity of the transmitted ECC code itself.
摘要翻译：根据本发明的系统和方法产生在y位域中发送的ECC码，以及从本机x位域转换到y位域的数据。这样的系统和方法提供作为允许时钟恢复并且可以使用奇偶校验或其他方法来验证所发送的ECC代码本身的完整性的传输串行流的一部分的ECC代码的表示。

7. 发明授权

US07734977B2 Method and system for error correction over serial link 有权
标题翻译：通过串行链路进行纠错的方法和系统
公开(公告)号：US07734977B2
公开(公告)日：2010-06-08
申请号：US10835711
申请日：2004-04-29
申请人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
发明人： Matthew D. Ornes , Christopher I. W. Norrie , Gene K. Chui
IPC分类号： H04L1/00
CPC分类号： H03M13/098 , H03M13/09
摘要： A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.
摘要翻译：根据本发明的系统和方法产生在y位域中发送的ECC码，并将数据从本机x位域转换为y位域。这样的系统和方法提供了ECC代码的表示，其是允许时钟恢复并且可以使用奇偶校验或其他方法来验证所发送的ECC代码本身的完整性的所发送的串行流的一部分。

8. 发明授权

US06223257B1 Instruction cache address generation technique having reduced delays in fetching missed data 失效
标题翻译：指令高速缓存地址生成技术减少了提取丢失数据的延迟
公开(公告)号：US06223257B1
公开(公告)日：2001-04-24
申请号：US09310659
申请日：1999-05-12
申请人： Sean P. Cummins , Kenneth K. Munson , Christopher I. W. Norrie , Matthew D. Ornes
发明人： Sean P. Cummins , Kenneth K. Munson , Christopher I. W. Norrie , Matthew D. Ornes
IPC分类号： G06F1212
CPC分类号： G06F9/3802 , G06F12/0859
摘要： A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory. This eliminates the occurrence of penalty delay cycles that reduce the rate at which instructions are issued in existing processors, and thus improves the speed of operation of the processors.
摘要翻译：一种用于以最小延迟从高速缓冲存储器读取指令数据的技术和系统。地址由流水线地址产生电路计算并在两个或多个周期内应用于高速缓冲存储器。虽然正在检索一个地址的数据，但是正在计算下一个地址。假设当计算下一个地址时，当前地址将返回其正在寻址的所有数据。响应于当高速缓存中没有当前地址上的数据时从高速缓存接收到的未命中信号，从主系统存储器读取丢失的数据并以改进的速度访问。在高速缓冲存储器和处理器以比主系统存储器更高的时钟频率工作的系统中，仅在周期性发生的高速缓存时钟周期期间从主存储器获得新的数据。错过的高速缓存存储器地址以在首次从主存储器可用的相同高速缓存时钟周期内访问这样的新数据的方式被重新生成。这消除了降低在现有处理器中发出指令的速率的惩罚延迟周期的发生，并因此提高了处理器的操作速度。

9. 发明授权

US5490255A Expedited execution of pipelined command having self-ordering operand processing requirements 失效
标题翻译：快速执行具有自订操作数处理要求的流水线命令
公开(公告)号：US5490255A
公开(公告)日：1996-02-06
申请号：US814878
申请日：1991-12-26
申请人： Stephen J. Rawlinson , Christopher I. W. Norrie
发明人： Stephen J. Rawlinson , Christopher I. W. Norrie
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30025 , G06F9/3824 , G06F9/383 , G06F9/3867
摘要： A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stage at a later time. The sidetracking mechanism is used to speed processing of rate-variable operand-consuming instructions such as the EDIT and EDMK commands.
摘要翻译：通过D，A，T，B，X和W级序列处理操作数数据的流水线计算机包括一个侧向队列。在X阶段准备好立即处理这样的数据之前提前退出B阶段的数据被保持在侧面队列中，并在稍后的时间被呈现给X阶段。旁路机制用于加速诸如EDIT和EDMK命令之类的速率变量操作使用指令的处理。

10. 发明授权

US07647438B1 Binary base address sorting method and device with shift vector 有权
标题翻译：二进制基地址排序方法和具有移位向量的设备
公开(公告)号：US07647438B1
公开(公告)日：2010-01-12
申请号：US11382480
申请日：2006-05-09
申请人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
发明人： Christopher I. W. Norrie , Christopher Bergen , Robert Divivier , Thomas J. Norrie
IPC分类号： G06F19/00 , G06F12/02
CPC分类号： G06F7/24
摘要： A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.
摘要翻译：公开了一种开关装置中的基地址分类装置，其包括基地址寄存器阵列，其中每个基地址寄存器包含基地址，地址移位装置; 以及控制逻辑元件，其电耦合到所述基地址寄存器阵列，并且在接收到包括新的基地址的配置命令时可操作以实现用于重新配置所述基地址寄存器阵列的内容的方法。该方法包括确定写入新基址的基地址寄存器阵列中的插入点基地址寄存器，将一个或多个基地址寄存器阵列的内容移位到其他基地址寄存器以保持排序顺序，将配置命令的内容插入到插入点基地址寄存器中。插入导致保留寄存器阵列内容的预定顺序。

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