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1. 发明授权

US08621318B1 Nonvolatile memory controller with error detection for concatenated error correction codes 有权
标题翻译：具有错误检测功能的非易失性存储器控制器，用于级联纠错码
公开(公告)号：US08621318B1
公开(公告)日：2013-12-31
申请号：US13435572
申请日：2012-03-30
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.
摘要翻译：一种非易失性存储器控制器，用于通过执行硬判决内纠错码解码和使用硬判决内纠错码解码解码的数据的外纠错码解码来恢复编码数据，然后确定编码数据是否已成功解码。如果编码数据尚未成功解码，则控制器使用软判决算法和使用软判决内部误差解码的数据的外部纠错码解码来对编码数据执行软判决内部纠错码解码校正码解码，然后确定编码数据是否已被成功解码。如果编码数据尚未成功解码，则控制器通过对编码数据执行RAID操作来恢复数据。

2. 发明授权

US08397144B1 BCH data correction system and method 有权
标题翻译： BCH数据校正系统及方法
公开(公告)号：US08397144B1
公开(公告)日：2013-03-12
申请号：US12913716
申请日：2010-10-27
申请人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
发明人： Christopher I. W. Norrie , Alessia Marelli , Rino Micheloni , Peter Z. Onufryk
IPC分类号： H03M13/00
CPC分类号： H03M13/6566 , H03M13/152 , H03M13/1555 , H03M13/6561
摘要： In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.
摘要翻译：在各种实施例中，数据校正系统具有包括搜索模块的数据路径。每个搜索模块具有用于基于定位多项式定位数据单元中的多个数据位错误的相应位错误容量。数据校正系统基于输入数据单元产生校正子，根据校正子产生定位多项式，并根据定位多项式确定输入数据单元中的数据位错误数。此外，数据校正系统选择搜索模块中的一个具有至少输入数据单元中的数据位错误数量的位错误容量。所选择的搜索模块基于定位多项式生成错误指示符。数据校正系统根据误差指示器校正输入数据单元中的每个数据位错误。

3. 发明授权

US08707122B1 Nonvolatile memory controller with two-stage error correction technique for enhanced reliability 有权
标题翻译：具有两级纠错技术的非易失性存储器控制器，增强可靠性
公开(公告)号：US08707122B1
公开(公告)日：2014-04-22
申请号：US13023336
申请日：2011-02-08
申请人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
发明人： Rino Micheloni , Peter Z. Onufryk , Alessia Marelli , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/2915 , G06F11/1012 , G06F11/108 , H03M13/098 , H03M13/152
摘要： A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.
摘要翻译：非易失性存储器控制器为数据条带中的每个数据单元生成纠错码，并且基于数据条带的数据单位生成奇偶校验单元。如果数据条带的数据单元具有不超过非易失性存储器控制器的纠错能力的多个数据位错误，则非易失性存储器控制器基于数据单元的纠错码来校正数据单元中的任何数据位错误。否则，如果数据条带的数据单元具有超过非易失性存储器控制器的纠错能力的数据位错误数，则非易失性存储器控制器基于数据条带和奇偶校验单元的其他数据单元来恢复数据单元。

4. 发明授权

US08656257B1 Nonvolatile memory controller with concatenated error correction codes 有权
标题翻译：具有级联纠错码的非易失性存储器控制器
公开(公告)号：US08656257B1
公开(公告)日：2014-02-18
申请号：US13434770
申请日：2012-03-29
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using the inner error correction code of the encoded data followed by the outer error correction code of the encoded data if it is determined that the correction capacity of the outer error correction code is exceeded. Additionally, if it is determined that the correction capacity of the outer error correction code is exceed after recovering the data using the inner error correction code, the nonvolatile memory storage module may perform a redundant array of independent disks (RAID) operation to recover the data.
摘要翻译：如果确定不超过外部纠错码的校正容量，则非易失性存储器控制器可以使用编码数据的外部纠错码来恢复编码数据。或者，如果确定超出了外部纠错码的校正容量，则非易失性存储器控制器可以使用编码数据的内部纠错码来跟踪编码数据的外部纠错码来恢复编码数据。此外，如果在使用内部纠错码恢复数据之后确定外部纠错码的校正能力超过，则非易失性存储器存储模块可以执行独立盘（RAID）冗余阵列操作以恢复数据。

5. 发明授权

US08694849B1 Shuffler error correction code system and method 有权
标题翻译：洗牌机纠错码系统及方法
公开(公告)号：US08694849B1
公开(公告)日：2014-04-08
申请号：US13330573
申请日：2011-12-19
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/1048 , G06F11/1076 , H03M13/152 , H03M13/19
摘要： A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.
摘要翻译：数据存储装置将数据单元与数据单元的纠错码单元一起存储在存储块的存储器页中。此外，数据存储装置将用于数据单元的纠错码单元存储在另一存储块的存储器页中。在各种实施例中，纠错码单元中的一个或两个形成用于校正数据单元中的数据位错误的纠错码。由于包含数据单元的存储器页面不具有用于同时存储纠错码和数据单元的存储容量，所以数据存储装置能够通过使用纠错码来校正数据单元中更大数量的数据位错误代码与使用适合内存页面的纠错码进行比较。

6. 发明授权

US08694855B1 Error correction code technique for improving read stress endurance 有权
标题翻译：纠错码技术，提高阅读耐力
公开(公告)号：US08694855B1
公开(公告)日：2014-04-08
申请号：US13287443
申请日：2011-11-02
申请人： Rino Micheloni , Luca Crippa , Alessia Marelli
发明人： Rino Micheloni , Luca Crippa , Alessia Marelli
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and generates a corrected data unit by correcting data bit errors in the data unit based on the error correction code if the number of data bit errors in the data unit does not exceed an error correction capacity of the error correction code. Otherwise, the data storage device generates a modified data unit based on the data unit by negating at least one erroneous data bit the data unit based on the bit error indicator and corrects any remaining data bit errors in the modified data unit based on the error correction code.
摘要翻译：数据存储装置从存储器页面读取数据单元，检测数据单元中的数据位错误的数量，并产生识别数据单元中的数据位错误的位索引的位错误指示符。数据存储装置再次从存储器页面读取数据单元，并且如果数据单元中的数据位错误的数目不超过数据单元，则通过校正数据单元中的数据位错误来校正数据单元，并产生校正的数据单元纠错码的纠错能力。否则，数据存储装置基于数据单元生成基于位错误指示符的数据单元的至少一个错误数据位的修正数据单元，并且基于纠错修正修改数据单元中的剩余数据位错误码。

7. 发明申请

US20110167318A1 READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE AND MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE 有权
标题翻译：具有嵌入式错误修正代码的存储器件和带有嵌入式错误校正代码的存储器件的读取方法
公开(公告)号：US20110167318A1
公开(公告)日：2011-07-07
申请号：US13047678
申请日：2011-03-14
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并且生成至少一个第二恢复串（S2-SN）。基于第一恢复串（S1）与第二恢复串恢复字符串（S2-SN），生成修改字符串（SM），其中存在擦除（X），并且使用修改字符串（SM）执行至少一个第二解码尝试。

8. 发明申请

US20080104477A1 Method for performing error corrections of digital information codified as a symbol sequence 有权
标题翻译：用于执行编码为符号序列的数字信息的纠错的方法
公开(公告)号：US20080104477A1
公开(公告)日：2008-05-01
申请号：US12001294
申请日：2007-12-10
申请人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1575 , H03M13/13 , H03M13/15 , H03M13/19
摘要： A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.
摘要翻译：描述了一种用于对编码为符号序列的数字信息进行纠错的方法和系统，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含一部分误差校正码的序列的传输，这更可能是通过使用在接收时要恢复的奇偶校验矩阵的误差校正子的计算来传送的。有利地，根据本发明的实施例，并入原始序列中的错误代码属于非布尔组。

9. 发明授权

US07328397B2 Method for performing error corrections of digital information codified as a symbol sequence 有权
公开(公告)号：US07328397B2
公开(公告)日：2008-02-05
申请号：US10805168
申请日：2004-03-19
申请人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： H03M13/00
CPC分类号： H03M13/1575 , H03M13/13 , H03M13/15 , H03M13/19
摘要： A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

10. 发明申请

US20070234164A1 Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
标题翻译：具有嵌入式纠错码的存储器件的读取方法和具有嵌入式纠错码的存储器件
公开(公告)号：US20070234164A1
公开(公告)日：2007-10-04
申请号：US11713376
申请日：2007-03-01
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A 0，A 1，...，ALS-1）的第一读取以产生第一恢复串 S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S 2 -SN）。基于第一恢复字符串（S 1）和第二恢复字符串（S 2 -SN）之间的比较，生成修饰字符串（SM），其中存在消息（X），并且至少一个第二使用修改的串（SM）进行解码尝试。

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