专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07490276B1 Testing self-repairing memory of a device 有权
标题翻译：测试设备的自修复内存
公开(公告)号：US07490276B1
公开(公告)日：2009-02-10
申请号：US11255383
申请日：2005-10-20
申请人： Christopher E. White , Steven C. McMahan , John K. Eitrheim
发明人： Christopher E. White , Steven C. McMahan , John K. Eitrheim
IPC分类号： G01C29/00 , G01R31/28
CPC分类号： G11C29/4401 , G11C29/24 , G11C29/44 , G11C29/787 , G11C2029/1208 , G11C2029/4402
摘要： Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.
摘要翻译：测试设备的一个或多个存储器包括从具有一个或多个存储器的设备的一个或多个内置自测试器接收一个或多个第一修复记录。一个内置的自测试器与一个内存相关联，第一个修复记录描述了一个内存的第一个修复。从第一修复记录生成与存储器中的第一修复对应的第一修复签名，然后记录。从内置自检器接收一个或多个第二修复记录，其中第二修复记录描述了在存储器处的第二修复。从第二修复记录生成与存储器中的第二修复相对应的第二修复签名。将第二修复签名与第一修复签名进行比较。响应于比较来评估该设备。

2. 发明授权

US07007211B1 Testing self-repairing memory of a device 有权
公开(公告)号：US07007211B1
公开(公告)日：2006-02-28
申请号：US10264551
申请日：2002-10-04
申请人： Christopher E. White , Steven C. McMahan , John K. Eitrheim
发明人： Christopher E. White , Steven C. McMahan , John K. Eitrheim
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/24 , G11C29/44 , G11C29/787 , G11C2029/1208 , G11C2029/4402
摘要： Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

3. 发明授权

US07739426B1 Descriptor transfer logic 有权
标题翻译：描述符传递逻辑
公开(公告)号：US07739426B1
公开(公告)日：2010-06-15
申请号：US11555066
申请日：2006-10-31
申请人： Donald E. Steiss , Christopher E. White , Jonathan Rosen , John A. Fingerhut , Barry S. Burns
发明人： Donald E. Steiss , Christopher E. White , Jonathan Rosen , John A. Fingerhut , Barry S. Burns
IPC分类号： G06F3/00
CPC分类号： H04L12/66
摘要： A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.
摘要翻译：处理引擎包括描述符传送逻辑，其接收由软件控制的通用处理元件生成的描述符。描述符传送逻辑管理将描述符发送到执行资源并响应于所发送的描述符从资源接收响应的事务。描述符传送逻辑可以管理启动事务的缓冲区和寄存器的分配和操作，跟踪事务的状态，以及代表通用处理单元从资源中回收所有响应。

4. 发明授权

US5734881A Detecting short branches in a prefetch buffer using target location information in a branch target cache 失效
标题翻译：使用分支目标缓存中的目标位置信息检测预取缓冲区中的短分支
公开(公告)号：US5734881A
公开(公告)日：1998-03-31
申请号：US572773
申请日：1995-12-15
申请人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
发明人： Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/30054 , G06F9/3806 , G06F9/3814
摘要： A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction. The exemplary prefetch unit uses a three-block prefetch buffer each storing a 16 byte (cache line) prefetch block--the three prefetch buffers are logically allocated for the current, next, and previous prefetch blocks, and the target of a short branch may be either forward or backward of the branch, and may reside in the same prefetch buffer as the branch (which logically will be current) or in a contiguous prefetch buffer (logically next or previous). Avoiding prefetch requests in the case of short branches reduces contention for cache access and associated bus traffic.
摘要翻译：流水线x86处理器包括预取单元（预取缓冲器）和协作以检测分支目标（指定为短分支）何时已经在预取缓冲器中的分支单元，从而避免发出预取请求以检索目标。分支单元包括分支目标高速缓存（BTC），除了用于预取包含目标指令的指令字节的预取块的目标地址信息之外，每个条目还存储预取块位置字段 - 当该字段有效时，其提供在预取块中已经在预取缓冲器中的短分支的目标指令的位置。响应于在BTC中击中的分支，如果相关联的预取块位置字段有效，则预取单元能够开始传送用于目标指令的指令字节，而不对包含目标指令的预取块发出预取请求。示例性预取单元使用三块预取缓冲器，每个存储16字节（高速缓存线）预取块 - 三个预取缓冲器在逻辑上分配给当前，下一个和先前的预取块，并且短分支的目标可以是分支的前向或后向，并且可以驻留在与分支（逻辑上将是当前）相同的预取缓冲器中，或者在连续的预取缓冲器（逻辑上是下一个或前一个）中。在短分支的情况下避免预取请求减少了缓存访问和相关总线流量的争用。

5. 发明授权

US5996071A Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address 失效
标题翻译：通过将锁存的存储地址与随后的目标地址进行比较，通过分支处理检测流水线处理器中的自修改代码
公开(公告)号：US5996071A
公开(公告)日：1999-11-30
申请号：US572996
申请日：1995-12-15
申请人： Christopher E. White , Antone L. Fourcroy
发明人： Christopher E. White , Antone L. Fourcroy
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3812 , G06F9/30054 , G06F9/3806
摘要： A pipelined x86 processor implements a method of detecting self-modifying code in which a prefetched block of instruction bytes may contain an instruction that is modified by a store instruction preceding it in the execution pipeline. The processor includes a Prefetch unit having a multi-block prefetch buffer, a Branch unit with a branch target cache (BTC), and a Load/Store (LDST) unit having store reservation stations. Self-modifying code is detected in three ways: (a) the Prefetch unit snoops store addresses from the LDST unit which are compared with (i) an address tag for each of the prefetch blocks of instruction bytes already loaded into the prefetch buffer, and (ii) the addresses of any pending prefetch requests, (b) the LDST unit snoops prefetch addresses issued by the Prefetch unit and compares them to store addresses queued in the store reservation stations, and (c) to ensure compatibility with the 486 specification for self-modifying code (which requires that a store that modifies an instruction be followed immediately by a jump to that instruction), the LDST unit detects when a store is followed by a COF that hits in the BTC which output a target address that is the same as the preceding store address. In particular, Prefetch unit snooping and LDST unit snooping detect instances of self-modifying code conditions that do not follow the 486 specification.
摘要翻译：流水线x86处理器实现检测自修改代码的方法，其中指令字节的预取块可以包含由执行流水线中的存储指令之前的存储指令修改的指令。处理器包括具有多块预取缓冲器的预取单元，具有分支目标高速缓存（BTC）的分支单元以及具有存储预留站的加载/存储（LDST）单元。以三种方式检测自修改代码：（a）预取单元侦听存储来自LDST单元的地址，其与（i）已经加载到预取缓冲器的指令字节的每个预取块的地址标签进行比较，以及（ii）任何待处理的预取请求的地址，（b）LDST单元侦听由预取单元发出的预取地址，并将其与存储在存储预留站中排队的地址进行比较，以及（c）确保与486规范的兼容性自修改代码（其要求立即通过跳转到该指令来修改指令的存储），LDST单元检测存储器之后是否在BTC中命中的COF，该COF输出目标地址是与前一个商店地址相同。特别是，预取单元侦听和LDST单元侦听检测不符合486规范的自修改代码条件的实例。

6. 发明授权

US5375216A Apparatus and method for optimizing performance of a cache memory in a data processing system 失效
标题翻译：用于优化数据处理系统中的高速缓冲存储器的性能的装置和方法
公开(公告)号：US5375216A
公开(公告)日：1994-12-20
申请号：US844011
申请日：1992-02-28
申请人： William C. Moyer , John H. Arends , Christopher E. White , Keith E. Diefendorff
发明人： William C. Moyer , John H. Arends , Christopher E. White , Keith E. Diefendorff
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/02
CPC分类号： G06F9/30047 , G06F12/0802 , G06F12/0804 , G06F12/0862 , G06F9/30043 , G06F9/30181 , G06F9/383 , G06F9/3842 , G06F9/3863 , G06F2212/6028
摘要： A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.
摘要翻译：在数据处理器（20）中实现用于允许对高速缓存存储器的更大用户控制的电路。高速缓存控制指令已被实现以在数据高速缓存单元（24）的数据高速缓存（54）中执行触摸负载，刷新和分配操作。控制指令由指令高速缓存单元（26）和定序器（34）两者解码，以向加载/存储单元（28）提供必要的控制和地址信息。加载/存储单元（28）排序每个指令的执行，并且在适当的时间点向数据高速缓存单元（24）提供必要的控制和地址信息。缓存控制逻辑（60）随后处理地址和控制信息以提供执行每个高速缓存控制指令所必需的外部信号。此外，高速缓存控制逻辑（60）提供允许用户知道何时执行高速缓存事务的外部传输代码信号。

7. 发明授权

US5701448A Detecting segment limit violations for branch target when the branch unit does not supply the linear address 失效
标题翻译：当分支单元不提供线性地址时，检测分支目标的段限制违例
公开(公告)号：US5701448A
公开(公告)日：1997-12-23
申请号：US572949
申请日：1995-12-15
申请人： Christopher E. White
发明人： Christopher E. White
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/3861
摘要： A pipelined 32 bit x86 processor including a prefetch unit and a branch unit. During sequential prefetching, the prefetch unit increments a prefetch physical address PFPA and a corresponding prefetch linear address PFLA--for each prefetch address, the PFLA is compared with the code segment limit linear address CSLA to determine if the corresponding prefetch block of 16 instruction bytes (cache line) contains the segment limit. If a COF hits in the branch unit, it outputs corresponding target address information used to generate a prefetch address--this target address information includes bits �11:0! of the target address (which are the same for the target physical address), i.e., the branch unit does not provide a full PFLA for comparison with the CSLA. Instead, the prefetch unit compares the low order bits �11:0! of the target address supplied by the branch unit with the CSLA--if a partial match occurs indicating that the CSLA address is potentially within such target prefetch block, the prefetch unit asserts a segment limit violation state that inhibits any instruction bytes from the target prefetch block from being transferred to the decoder. When the full target linear address is generated during the address calculation stage, it is compared with the CSLA address--(i) if they do not match, the segment limit violation state is deasserted, or (ii) if they match, the segment limit violation state is adjusted such that the transfer of instruction bytes from the target prefetch block is permitted up to the segment limit as represented by the CSLA address, and then a segment limit violation is signaled.
摘要翻译：一个流水线32位x86处理器，包括预取单元和分支单元。在顺序预取期间，预取单元为每个预取地址增加预取物理地址PFPA和相应的预取线性地址PFLA，将PFLA与代码段限制线性地址CSLA进行比较，以确定16个指令字节的相应预取块（缓存行）包含段限制。如果COF在分支单元中击中，则输出用于生成预取地址的相应的目标地址信息 - 该目标地址信息包括目标地址的位[11：0]（对于目标物理地址是相同的），即，分支机构不提供完整的PFLA来与CSLA进行比较。相反，预取单元将由分支单元提供的目标地址的低位比特[11：0]与CSLA进行比较 - 如果发生部分匹配指示CSLA地址潜在地在该目标预取块内，则预取单元断言阻止来自目标预取块的任何指令字节被传送到解码器的段限制违反状态。当在地址计算阶段产生全目标线性地址时，将其与CSLA地址（i）进行比较，如果它们不匹配，则段限制违反状态被断言，或者（ii）如果匹配，则段限制调整违反状态，使得从目标预取块传送指令字节允许直到由CSLA地址表示的段限制，然后发出段限制违例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式