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    • 1. 发明授权
      US5996071A Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address 失效
    • Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address
    • 通过将锁存的存储地址与随后的目标地址进行比较，通过分支处理检测流水线处理器中的自修改代码
    • US5996071A
    • 1999-11-30
    • US572996
    • 1995-12-15
    • Christopher E. White , Antone L. Fourcroy
    • Christopher E. White , Antone L. Fourcroy
    • G06F9/38 , G06F9/42
    • G06F9/3812 , G06F9/30054 , G06F9/3806
    • A pipelined x86 processor implements a method of detecting self-modifying code in which a prefetched block of instruction bytes may contain an instruction that is modified by a store instruction preceding it in the execution pipeline. The processor includes a Prefetch unit having a multi-block prefetch buffer, a Branch unit with a branch target cache (BTC), and a Load/Store (LDST) unit having store reservation stations. Self-modifying code is detected in three ways: (a) the Prefetch unit snoops store addresses from the LDST unit which are compared with (i) an address tag for each of the prefetch blocks of instruction bytes already loaded into the prefetch buffer, and (ii) the addresses of any pending prefetch requests, (b) the LDST unit snoops prefetch addresses issued by the Prefetch unit and compares them to store addresses queued in the store reservation stations, and (c) to ensure compatibility with the 486 specification for self-modifying code (which requires that a store that modifies an instruction be followed immediately by a jump to that instruction), the LDST unit detects when a store is followed by a COF that hits in the BTC which output a target address that is the same as the preceding store address. In particular, Prefetch unit snooping and LDST unit snooping detect instances of self-modifying code conditions that do not follow the 486 specification.
    • 流水线x86处理器实现检测自修改代码的方法，其中指令字节的预取块可以包含由执行流水线中的存储指令之前的存储指令修改的指令。 处理器包括具有多块预取缓冲器的预取单元，具有分支目标高速缓存（BTC）的分支单元以及具有存储预留站的加载/存储（LDST）单元。 以三种方式检测自修改代码：（a）预取单元侦听存储来自LDST单元的地址，其与（i）已经加载到预取缓冲器的指令字节的每个预取块的地址标签进行比较，以及 （ii）任何待处理的预取请求的地址，（b）LDST单元侦听由预取单元发出的预取地址，并将其与存储在存储预留站中排队的地址进行比较，以及（c）确保与486规范的兼容性 自修改代码（其要求立即通过跳转到该指令来修改指令的存储），LDST单元检测存储器之后是否在BTC中命中的COF，该COF输出目标地址是 与前一个商店地址相同。 特别是，预取单元侦听和LDST单元侦听检测不符合486规范的自修改代码条件的实例。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5734881A Detecting short branches in a prefetch buffer using target location information in a branch target cache 失效
    • Detecting short branches in a prefetch buffer using target location information in a branch target cache
    • 使用分支目标缓存中的目标位置信息检测预取缓冲区中的短分支
    • US5734881A
    • 1998-03-31
    • US572773
    • 1995-12-15
    • Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
    • Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
    • G06F9/38
    • G06F9/3812 , G06F9/30054 , G06F9/3806 , G06F9/3814
    • A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction. The exemplary prefetch unit uses a three-block prefetch buffer each storing a 16 byte (cache line) prefetch block--the three prefetch buffers are logically allocated for the current, next, and previous prefetch blocks, and the target of a short branch may be either forward or backward of the branch, and may reside in the same prefetch buffer as the branch (which logically will be current) or in a contiguous prefetch buffer (logically next or previous). Avoiding prefetch requests in the case of short branches reduces contention for cache access and associated bus traffic.
    • 流水线x86处理器包括预取单元（预取缓冲器）和协作以检测分支目标（指定为短分支）何时已经在预取缓冲器中的分支单元，从而避免发出预取请求以检索目标。 分支单元包括分支目标高速缓存（BTC），除了用于预取包含目标指令的指令字节的预取块的目标地址信息之外，每个条目还存储预取块位置字段 - 当该字段有效时，其提供 在预取块中已经在预取缓冲器中的短分支的目标指令的位置。 响应于在BTC中击中的分支，如果相关联的预取块位置字段有效，则预取单元能够开始传送用于目标指令的指令字节，而不对包含目标指令的预取块发出预取请求。 示例性预取单元使用三块预取缓冲器，每个存储16字节（高速缓存线）预取块 - 三个预取缓冲器在逻辑上分配给当前，下一个和先前的预取块，并且短分支的目标可以是 分支的前向或后向，并且可以驻留在与分支（逻辑上将是当前）相同的预取缓冲器中，或者在连续的预取缓冲器（逻辑上是下一个或前一个）中。 在短分支的情况下避免预取请求减少了缓存访问和相关总线流量的争用。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US4931748A Integrated circuit with clock generator 失效
    • Integrated circuit with clock generator
    • 集成电路与时钟发生器
    • US4931748A
    • 1990-06-05
    • US364510
    • 1989-06-09
    • Mark W. McDermott , Antone L. Fourcroy
    • Mark W. McDermott , Antone L. Fourcroy
    • G01R29/027 , G06F1/04 , H03L7/14
    • H03L7/14 , G01R29/0273 , G06F1/04
    • A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.
    • 包括取决于外部提供的参考信号的时钟发生器电路的微处理器或其他集成电路包括检测该外部提供的参考信号的损耗并产生替代时钟信号的能力，尽管参考的丢失。 在特定实施例中，时钟发生器包括锁相环频率合成器，其通常依赖于外部晶体振荡器用于其参考频率信号。 发生器包括用于检测晶体信号中的异常并将频率合成器的压控振荡器切换到内部产生的参考电压的电路。 在特定实施例中，时钟发生器还能够响应于参考信号的丢失而产生复位信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5860105A NDIRTY cache line lookahead 失效
    • NDIRTY cache line lookahead
    • NDIRTY高速缓存行前瞻
    • US5860105A
    • 1999-01-12
    • US557977
    • 1995-11-13
    • Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
    • Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
    • G06F12/08 , G06F12/00
    • G06F12/0804 , G06F12/0891
    • An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead. The cache line lookahead technique reduces the number of cache line accesses required during flush/export operations, with the attendant advantages of reduced flush/export penalty cycles and power, thereby improving overall system performance.
    • NDIRTY高速缓存行前瞻技术用于通过提供一种机制来避免扫描至少一些不包含脏数据的缓存行（因此不必被导出）来加速缓存刷新和导出操作。 示例性高速缓存组织使用单行前瞻，其中每个高速缓存行但最后一行与其相关联的NDIRTY位指示下一个高速缓存行是否包含脏数据。 对于缓存刷新和导出操作，当读取高速缓存行（N）以检查必须导出的脏数据时，还会测试该高速缓存行的NDIRTY位，以确定下一个高速缓存行（N + 1）是否包含脏 数据 - 如果NDIRTY位清除，表示下一个高速缓存行是干净的，那么该行被跳过，扫描将继续进行（N + 2）之后的行。 这种示例性的单行前瞻实现可以容易地扩展到N行前瞻。 高速缓存行前瞻技术减少了刷新/导出操作期间所需的高速缓存行访问次数，同时具有降低冲洗/导出惩罚周期和功率的优点，从而提高了整体系统性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5361392A Digital computing system with low power mode and special bus cycle therefor 失效
    • Digital computing system with low power mode and special bus cycle therefor
    • 具有低功耗模式和特殊总线周期的数字计算系统
    • US5361392A
    • 1994-11-01
    • US033992
    • 1993-03-19
    • Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
    • Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
    • G06F1/04 , G06F1/32 , G06F15/78 , G06F9/30 , G06F9/46 , G06F11/20 , G06F13/24
    • G06F9/30083 , G06F1/3203 , G06F9/30167
    • A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active. The active sub-system performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode. Only if the priority level of an interrupt is sufficiently high are the clock signals resumed, thus terminating the low power mode.
    • 具有低功率操作模式的数字计算系统包括用于在进入低功率模式之前通信的信息，该信息确定哪些事件将能够导致低功率模式的终止。 响应于执行LPSTOP指令，集成电路微计算机进入低功率模式。 只有重置事件和具有足够高的优先级才能通过中断掩码的中断事件才能导致低功率模式的终止。 LPSTOP指令将立即数据加载到状态寄存器中，复位中断屏蔽位。 然后通过专用总线周期将中断屏蔽写入微机内的子系统中的中断屏蔽寄存器。 该子系统然后将时钟信号关闭到微计算机的其余部分，只剩下这个子系统。 在低功耗模式下，有源子系统对接收到的中断请求的优先级进行中断屏蔽的比较。 只有当中断的优先级足够高时，恢复时钟信号，从而终止低功耗模式。
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