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1. 发明授权

US06673681B2 Process for forming MOS-gated power device having segmented trench and extended doping zone 有权
标题翻译：用于形成具有分段沟槽和延伸掺杂区的MOS门控功率器件的工艺
公开(公告)号：US06673681B2
公开(公告)日：2004-01-06
申请号：US10174641
申请日：2002-06-19
申请人： Christopher B. Kocon , Thomas E. Grebs , Joseph L. Cumbo , Rodney S. Ridley
发明人： Christopher B. Kocon , Thomas E. Grebs , Joseph L. Cumbo , Rodney S. Ridley
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66348 , H01L29/7397 , H01L29/749 , H01L2924/0002 , H01L2924/00
摘要： A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.
摘要翻译：用于构造沟槽MOS门控器件的工艺包括：在半导体衬底中形成包括上部段和底部段的延伸沟槽，其中底部区段相对于沟槽上段的较大宽度具有较小的宽度，并且延伸达到对应于延伸沟槽的总深度的深度。沟槽的底部段基本上被介电材料填充。沟槽上段具有包括电介质材料的底板和侧壁，并且基本上填充有导电材料以形成栅极区域。第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域形成在与延伸掺杂区域相对的延伸沟槽侧的表面阱区域中。

2. 发明授权

US06433385B1 MOS-gated power device having segmented trench and extended doping zone and process for forming same 有权
标题翻译：具有分段沟槽和延伸掺杂区的MOS门控功率器件及其形成工艺
公开(公告)号：US06433385B1
公开(公告)日：2002-08-13
申请号：US09689939
申请日：2000-10-12
申请人： Christopher B. Kocon , Thomas E. Grebs , Joseph L. Cumbo , Rodney S. Ridley
发明人： Christopher B. Kocon , Thomas E. Grebs , Joseph L. Cumbo , Rodney S. Ridley
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66348 , H01L29/7397 , H01L29/749 , H01L2924/0002 , H01L2924/00
摘要： A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.
摘要翻译：沟槽MOS门控器件包括掺杂的单晶半导体衬底，其包括上层并且是第一导电类型。在上层中的衬底中的延伸沟槽包括相对于彼此具有不同宽度的两个区段：填充有介电材料的较小宽度的底部区段和宽度较大的上部区段，其内衬有电介质材料并基本上填充有导电材料，填充的沟槽的上部段形成栅极区域。第二相对导电类型的扩展掺杂区仅在沟槽的一侧从上表面延伸到衬底的上层，并且覆盖第一导电类型的漏极区的第二导电类型的掺杂阱区是设置在沟槽相对侧的上层中。

3. 发明授权

US06602768B2 MOS-gated power device with doped polysilicon body and process for forming same 失效
公开(公告)号：US06602768B2
公开(公告)日：2003-08-05
申请号：US10044768
申请日：2002-01-10
申请人： Christopher B. Kocon , Rodney S. Ridley , Thomas E. Grebs
发明人： Christopher B. Kocon , Rodney S. Ridley , Thomas E. Grebs
IPC分类号： H01L2104
CPC分类号： H01L29/7816 , H01L29/04 , H01L29/1095 , H01L29/7395 , H01L29/7801 , H01L29/7813 , Y10S438/914
摘要： An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.

4. 发明授权

US08143123B2 Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices 有权
标题翻译：在功率半导体器件中形成多晶硅介电层（IPD）层的方法
公开(公告)号：US08143123B2
公开(公告)日：2012-03-27
申请号：US12041546
申请日：2008-03-03
申请人： Thomas E. Grebs , Rodney S. Ridley , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Christopher B. Kocon
发明人： Thomas E. Grebs , Rodney S. Ridley , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Christopher B. Kocon
IPC分类号： H01L21/336
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.
摘要翻译：一种用于形成在沟槽内具有电极间电介质（IPD）层的功率半导体器件的方法，包括：提供具有沟槽的半导体衬底，用第一层介电材料衬套沟槽的侧壁和底部，第一层导电材料以形成第一电极，将第一层介电材料和第一导电材料层凹入沟槽内的第一深度，在介电材料的顶表面上形成多晶硅材料层和导电材料在沟槽内部氧化多晶硅材料层，以及在氧化层顶部的沟槽内部形成第二电极，并通过第二介电层与沟槽侧壁隔离。通过化学或物理地改变顶部多晶硅，例如通过注入杂质，可以增强氧化步骤。

5. 发明申请

US20080199997A1 Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices 有权
标题翻译：在功率半导体器件中形成多聚电介质（IPD）层的方法
公开(公告)号：US20080199997A1
公开(公告)日：2008-08-21
申请号：US12041546
申请日：2008-03-03
申请人： Thomas E. Grebs , Rodney S. Ridley , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Christopher B. Kocon
发明人： Thomas E. Grebs , Rodney S. Ridley , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Christopher B. Kocon
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.
摘要翻译：一种用于形成在沟槽内具有电极间电介质（IPD）层的功率半导体器件的方法，包括：提供具有沟槽的半导体衬底，用第一层介电材料衬套沟槽的侧壁和底部，第一层导电材料以形成第一电极，将第一层介电材料和第一导电材料层凹入沟槽内的第一深度，在介电材料的顶表面上形成多晶硅材料层和导电材料在沟槽内部氧化多晶硅材料层，以及在氧化层顶部的沟槽内部形成第二电极，并通过第二介电层与沟槽侧壁隔离。通过化学或物理地改变顶部多晶硅，例如通过注入杂质，可以增强氧化步骤。

6. 发明授权

US06818947B2 Buried gate-field termination structure 有权
标题翻译：埋地栅场终端结构
公开(公告)号：US06818947B2
公开(公告)日：2004-11-16
申请号：US10247464
申请日：2002-09-19
申请人： Thomas E. Grebs , Christopher B. Kocon , Rodney S. Ridley, Sr. , Gary M. Dolny , Nathan Lawrence Kraft , Louise E. Skurkey
发明人： Thomas E. Grebs , Christopher B. Kocon , Rodney S. Ridley, Sr. , Gary M. Dolny , Nathan Lawrence Kraft , Louise E. Skurkey
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： In a power semiconductor device 10, a continuous trench has an outer circumferential portion 58 that includes a field plate and inner portions 28 that carry include one or more gate runners 34 to that the gate runners and the field plate are integral with each other. The trench structure 58, 28 is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.
摘要翻译：在功率半导体器件10中，连续沟槽具有包括场板的外周部58和承载包括一个或多个栅极流道34的内部部分28，使得栅极流道和场板彼此成一体。沟槽结构58,28更容易形成和占据现有技术的分离结构的较小的表面空间。沟槽衬有绝缘体，并进一步填充导电多晶硅和顶绝缘体。

7. 发明授权

US07416948B2 Trench FET with improved body to gate alignment 有权
标题翻译：沟槽FET具有改善的体对门对准
公开(公告)号：US07416948B2
公开(公告)日：2008-08-26
申请号：US11551992
申请日：2006-10-23
申请人： Nathan L. Kraft , Ashok Challa , Steven P. Sapp , Hamza Yilmaz , Daniel Calafut , Dean E. Probst , Rodney S. Ridley , Thomas E. Grebs , Christopher B. Kocon , Joseph A. Yedinak , Gary M. Dolny
发明人： Nathan L. Kraft , Ashok Challa , Steven P. Sapp , Hamza Yilmaz , Daniel Calafut , Dean E. Probst , Rodney S. Ridley , Thomas E. Grebs , Christopher B. Kocon , Joseph A. Yedinak , Gary M. Dolny
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.
摘要翻译：场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。每个沟槽部分地填充有一种或多种材料。执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。然后在每个身体区域中形成第一导电类型的源区域。

8. 发明申请

US20080150020A1 Trenched Shield Gate Power Semiconductor Devices and Methods of Manufacture 有权
标题翻译：宽屏蔽门功率半导体器件及其制造方法
公开(公告)号：US20080150020A1
公开(公告)日：2008-06-26
申请号：US12018166
申请日：2008-01-22
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J. G. Lee , Peter H. Wilson , Joseph A. Yedinak , J. Y. Jung , H. C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J. G. Lee , Peter H. Wilson , Joseph A. Yedinak , J. Y. Jung , H. C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L29/78
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode. The first conductive layer inside the active trench can form a secondary gate electrode that is configured to be electrically biased to a desired potential. The semiconductor device can also include a Schottky structure formed between the charge control trench and a second adjacent charge control trench.
摘要翻译：半导体功率器件包括第一导电类型的漂移区域，在漂移区域上方延伸并且具有与第一导电类型相反的第二导电类型的阱区域，延伸穿过阱区域并进入漂移区域的有源沟槽。主要沟槽包括侧壁和衬底与介电材料的底部，其基本上被第一导电层和第二导电层填充。第二导电层形成栅极，并且设置在第一导电层的上方，并且通过电极间电介质材料与第一导电层分离。该器件还包括形成在阱区内并且邻近有源沟槽的第一导电类型的源极区域以及充电控制沟槽，该电荷控制沟槽比有源沟槽更深地延伸到漂移区域中，并且基本上填充有材料以允许垂直电荷控制漂移区域。电荷控制沟槽可以衬有介电材料层并且基本上填充有导电材料。有源沟槽可以包括由设置在第一屏蔽电极下方的导电材料制成的第二屏蔽电极。有源沟槽内的第一导电层可以形成辅助栅电极，其被配置为电偏置到期望的电位。半导体器件还可以包括形成在电荷控制沟槽和第二相邻电荷控制沟槽之间的肖特基结构。

9. 发明申请

US20120220091A1 METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER 有权
标题翻译：制造具有厚底层氧化层的功率半导体器件的方法
公开(公告)号：US20120220091A1
公开(公告)日：2012-08-30
申请号：US13418128
申请日：2012-03-12
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L21/336 , H01L21/311
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
摘要翻译：在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括通过填充沟槽并覆盖衬底顶表面的亚大气压化学气相沉积工艺形成共形氧化膜。该方法还包括将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。

10. 发明授权

US06365942B1 MOS-gated power device with doped polysilicon body and process for forming same 有权
标题翻译：具有掺杂多晶硅体的MOS门控功率器件及其形成工艺
公开(公告)号：US06365942B1
公开(公告)日：2002-04-02
申请号：US09731169
申请日：2000-12-06
申请人： Christopher B. Kocon , Rodney S. Ridley , Thomas E. Grebs
发明人： Christopher B. Kocon , Rodney S. Ridley , Thomas E. Grebs
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L29/04 , H01L29/1095 , H01L29/7395 , H01L29/7801 , H01L29/7813 , Y10S438/914
摘要： An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.
摘要翻译：具有衬底101的改进的MOS门控功率器件300，衬底101具有包括第二导电类型的掺杂阱区107的第一导电类型的掺杂单晶硅的上层101a。衬底还包括设置在上层的上表面的阱区107中的至少一个第一导电类型的重掺杂源极区111，栅极区106具有通过电介质与源极区域电绝缘的导电材料105 材料，覆盖栅极和源极区域114的上表面上的图案化层间电介质层112以及第一导电类型115的重掺杂漏极区域。改进包括主体区域301，其包含设置在第二导电类型115中的第二导电类型的重掺杂多晶硅在单晶衬底的上表面处的阱区107。

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