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1. 发明申请

US20130194564A1 METHOD AND APPARATUS FOR MEASURING PHOTOVOLTAIC CELLS 审中-公开
标题翻译：用于测量光伏电池的方法和装置
公开(公告)号：US20130194564A1
公开(公告)日：2013-08-01
申请号：US13358706
申请日：2012-01-26
申请人： Chris Stapelmann , Johannes Kirchner
发明人： Chris Stapelmann , Johannes Kirchner
IPC分类号： G01J3/28
CPC分类号： G01J3/28 , G01J1/08 , H02S50/10
摘要： A solar simulator is disclosed having a test chamber for receiving a photovoltaic device for testing, an illumination source for selectively illuminating the photovoltaic device to produce a test signal therefrom, a spectrophotometer for providing a measurement of the spectral distribution of the output of the illumination source, a database containing spectral response information of monitor cell, reference device and DUT, and a computation device for receiving said test signal and said measurement, wherein the computation device converts said test signal into a test value based on said measurement.
摘要翻译：公开了一种太阳能模拟器，其具有用于接收用于测试的光伏器件的测试室，用于选择性地照射光伏器件以产生测试信号的照明源，用于提供照明源的输出的光谱分布的测量的分光光度计，包含监视单元，参考装置和DUT的频谱响应信息的数据库以及用于接收所述测试信号和所述测量的计算装置，其中所述计算装置基于所述测量将所述测试信号转换成测试值。

2. 发明申请

US20090114955A1 Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure 有权
标题翻译：制造鳍形半导体结构和鳍形半导体结构的方法
公开(公告)号：US20090114955A1
公开(公告)日：2009-05-07
申请号：US11934665
申请日：2007-11-02
申请人： Chris Stapelmann , Thomas Schulz
发明人： Chris Stapelmann , Thomas Schulz
IPC分类号： H01L29/04 , H01L21/20 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/045 , H01L29/66795 , H01L29/7843 , H01L29/7845 , H01L29/785
摘要： A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.
摘要翻译：鳍状结构由半导体材料形成。处理鳍状结构以沿着翅片的纵向方向在半导体材料内产生拉伸应变。

3. 发明申请

US20070205489A1 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US20070205489A1
公开(公告)日：2007-09-06
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

4. 发明申请

US20090179308A1 Method of Manufacturing a Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090179308A1
公开(公告)日：2009-07-16
申请号：US12013923
申请日：2008-01-14
申请人： Chris Stapelmann
发明人： Chris Stapelmann
IPC分类号： H01L23/58 , H01L21/00 , H01L21/425 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/268 , H01L21/2686 , H01L29/7843
摘要： According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner.
摘要翻译：根据本发明的一个实施例，提供一种制造半导体器件的方法。该方法包括：形成半导体结构; 在半导体结构上形成应力衬垫; 并改变应力衬里的至少一部分的应力特性。

5. 发明授权

US08501632B2 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US08501632B2
公开(公告)日：2013-08-06
申请号：US11312878
申请日：2005-12-20
申请人： Chris Stapelmann , Armin Tilke
发明人： Chris Stapelmann , Armin Tilke
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , H01L21/0217 , H01L21/0234 , H01L21/02348 , H01L21/3105 , H01L21/3141 , H01L21/3185 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。优选实施例包括在工件中形成至少一个沟槽，以及在所述至少一个沟槽的侧壁和底表面上以及使用原子层沉积（ALD）在工件的顶表面上方形成薄氮化物衬垫。绝缘材料沉积在工件的顶表面上，填充至少一个沟槽。绝缘材料的至少一部分从工件的顶表面上去除。在从工件的上表面上除去绝缘材料的至少一部分之后，至少一个沟槽中的薄氮化物衬垫至少与工件的顶表面共面。薄氮化物衬垫和绝缘材料形成半导体器件的隔离区域。

6. 发明申请

US20100297818A1 Semiconductor Devices Having pFET with SiGe Gate Electrode and Embedded SiGe Source/Drain Regions and Methods of Making the Same 有权
标题翻译：具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域及其制造方法的半导体器件
公开(公告)号：US20100297818A1
公开(公告)日：2010-11-25
申请号：US12850119
申请日：2010-08-04
申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
发明人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
摘要翻译：在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

7. 发明授权

US07800182B2 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same 有权
标题翻译：具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US07800182B2
公开(公告)日：2010-09-21
申请号：US11602117
申请日：2006-11-20
申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
发明人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
IPC分类号： H01L23/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
摘要翻译：在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

8. 发明授权

US07635634B2 Dielectric apparatus and associated methods 有权
标题翻译：电介质仪器及相关方法
公开(公告)号：US07635634B2
公开(公告)日：2009-12-22
申请号：US11735607
申请日：2007-04-16
申请人： Chris Stapelmann , Gert Jaschke , Armin Tilke
发明人： Chris Stapelmann , Gert Jaschke , Armin Tilke
IPC分类号： B05D5/12 , H01L21/8242
CPC分类号： H01L21/02356 , H01L21/02142 , H01L21/02164 , H01L21/02172 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/3141 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.
摘要翻译：在本发明的一个实施例中，在衬底上选择性地形成非晶相介质材料。然后将非晶相介电材料转化为结晶相电介质材料。

9. 发明申请

US20080290425A1 Method for Fabricating a Semiconductor Element, and Semiconductor Element 有权
标题翻译：半导体元件的制造方法以及半导体元件
公开(公告)号：US20080290425A1
公开(公告)日：2008-11-27
申请号：US12119972
申请日：2008-05-13
申请人： Luis-Felipe Giles , Thomas Hoffmann , Chris Stapelmann
发明人： Luis-Felipe Giles , Thomas Hoffmann , Chris Stapelmann
IPC分类号： H01L29/00 , H01L21/425 , H01L21/336
CPC分类号： H01L21/3223 , H01L21/263 , H01L21/26506 , H01L29/66575 , H01L29/78
摘要： In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
摘要翻译：在衬底中制造半导体元件的方法中，将第一注入离子注入到衬底中，从而在衬底的第一部分区域中产生微腔。此外，将非晶化离子注入到基板中，由此基板的第二部分区域至少部分非晶化，并且由此在基板中产生晶体缺陷。此外，第二注入离子注入基片的第二部分区域。此外，加热衬底，使得使用第二注入离子去除至少一些晶体缺陷。此外，掺杂剂原子被注入到衬底的第二部分区域中，其中使用掺杂剂原子形成半导体元件。

10. 发明授权

US08936995B2 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US08936995B2
公开(公告)日：2015-01-20
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
IPC分类号： H01L21/762 , H01L21/77
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

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