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1. 发明申请

US20070205489A1 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US20070205489A1
公开(公告)日：2007-09-06
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

2. 发明授权

US08936995B2 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US08936995B2
公开(公告)日：2015-01-20
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
IPC分类号： H01L21/762 , H01L21/77
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

3. 发明授权

US08501632B2 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US08501632B2
公开(公告)日：2013-08-06
申请号：US11312878
申请日：2005-12-20
申请人： Chris Stapelmann , Armin Tilke
发明人： Chris Stapelmann , Armin Tilke
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , H01L21/0217 , H01L21/0234 , H01L21/02348 , H01L21/3105 , H01L21/3141 , H01L21/3185 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。优选实施例包括在工件中形成至少一个沟槽，以及在所述至少一个沟槽的侧壁和底表面上以及使用原子层沉积（ALD）在工件的顶表面上方形成薄氮化物衬垫。绝缘材料沉积在工件的顶表面上，填充至少一个沟槽。绝缘材料的至少一部分从工件的顶表面上去除。在从工件的上表面上除去绝缘材料的至少一部分之后，至少一个沟槽中的薄氮化物衬垫至少与工件的顶表面共面。薄氮化物衬垫和绝缘材料形成半导体器件的隔离区域。

4. 发明授权

US07635634B2 Dielectric apparatus and associated methods 有权
标题翻译：电介质仪器及相关方法
公开(公告)号：US07635634B2
公开(公告)日：2009-12-22
申请号：US11735607
申请日：2007-04-16
申请人： Chris Stapelmann , Gert Jaschke , Armin Tilke
发明人： Chris Stapelmann , Gert Jaschke , Armin Tilke
IPC分类号： B05D5/12 , H01L21/8242
CPC分类号： H01L21/02356 , H01L21/02142 , H01L21/02164 , H01L21/02172 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/3141 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.
摘要翻译：在本发明的一个实施例中，在衬底上选择性地形成非晶相介质材料。然后将非晶相介电材料转化为结晶相电介质材料。

5. 发明申请

US20070141852A1 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US20070141852A1
公开(公告)日：2007-06-21
申请号：US11312878
申请日：2005-12-20
申请人： Chris Stapelmann , Armin Tilke
发明人： Chris Stapelmann , Armin Tilke
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , H01L21/0217 , H01L21/0234 , H01L21/02348 , H01L21/3105 , H01L21/3141 , H01L21/3185 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。优选实施例包括在工件中形成至少一个沟槽，以及在所述至少一个沟槽的侧壁和底表面上以及使用原子层沉积（ALD）在工件的顶表面上方形成薄氮化物衬垫。绝缘材料沉积在工件的顶表面上，填充至少一个沟槽。绝缘材料的至少一部分从工件的顶表面上去除。在从工件的上表面上除去绝缘材料的至少一部分之后，至少一个沟槽中的薄氮化物衬垫至少与工件的顶表面共面。薄氮化物衬垫和绝缘材料形成半导体器件的隔离区域。

6. 发明申请

US20080254204A1 DIELECTRIC APPARATUS AND ASSOCIATED METHODS 有权
标题翻译：电介质和相关方法
公开(公告)号：US20080254204A1
公开(公告)日：2008-10-16
申请号：US11735607
申请日：2007-04-16
申请人： Chris Stapelmann , Gert Jaschke , Armin Tilke
发明人： Chris Stapelmann , Gert Jaschke , Armin Tilke
IPC分类号： B05D5/12
CPC分类号： H01L21/02356 , H01L21/02142 , H01L21/02164 , H01L21/02172 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/3141 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.
摘要翻译：在本发明的一个实施例中，在衬底上选择性地形成非晶相介质材料。然后将非晶相介电材料转化为结晶相电介质材料。

7. 发明申请

US20070059897A1 Isolation for semiconductor devices 审中-公开
标题翻译：半导体器件隔离
公开(公告)号：US20070059897A1
公开(公告)日：2007-03-15
申请号：US11223232
申请日：2005-09-09
申请人： Armin Tilke , Bee Hong
发明人： Armin Tilke , Bee Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/3065 , H01L21/3086
摘要： Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to further scale the size of semiconductor devices. A first etch process is used to form a first trench portion, and a second etch process or an oxidation process is used to form a second trench portion beneath the first trench portion. The second trench portion is wider than the first trench portion. A liner may form during the first trench portion on the sidewalls of the first trench portion that protects the first trench portion sidewalls during the second etch process, in one embodiment. Alternatively, a liner may be deposited on the sidewalls of the first trench portion, in another embodiment.
摘要翻译：公开了用于半导体器件的隔离结构的形成方法和结构。隔离结构在底部比在顶部更宽，提供了进一步缩小半导体器件尺寸的能力。第一蚀刻工艺用于形成第一沟槽部分，并且第二蚀刻工艺或氧化工艺用于在第一沟槽部分下方形成第二沟槽部分。第二沟槽部分比第一沟槽部分宽。在一个实施例中，衬垫可以在第一沟槽部分的侧壁处的第一沟槽部分期间形成，其在第二蚀刻工艺期间保护第一沟槽部分侧壁。或者，在另一个实施例中，衬垫可以沉积在第一沟槽部分的侧壁上。

8. 发明申请

US20070042588A1 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US20070042588A1
公开(公告)日：2007-02-22
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

9. 发明授权

US08530355B2 Mixed orientation semiconductor device and method 有权
标题翻译：混合取向半导体器件及方法
公开(公告)号：US08530355B2
公开(公告)日：2013-09-10
申请号：US11317737
申请日：2005-12-23
申请人： Jiang Yan , Danny Pak-Chum Shum , Armin Tilke
发明人： Jiang Yan , Danny Pak-Chum Shum , Armin Tilke
IPC分类号： H01L21/311
CPC分类号： H01L27/092 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
摘要翻译：制造半导体器件的方法从半导体晶片开始，半导体晶片包括覆盖第二半导体层的第一半导体层。在半导体晶片中蚀刻第一沟槽。第一个沟槽填充绝缘材料。在第一沟槽内蚀刻第二沟槽并穿过绝缘材料，使得绝缘材料沿着第一沟槽的侧壁保留。第二沟槽露出第二绝缘层的一部分。然后可以使用第二半导体层作为种子层在第二沟槽内生长半导体层。

10. 发明授权

US08115279B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08115279B2
公开(公告)日：2012-02-14
申请号：US12769271
申请日：2010-04-28
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/06
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

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