专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07541290B2 Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing 有权
标题翻译：在半导体晶片上形成掩模图案的方法，其补偿在光刻处理期间的不均匀的中心到边缘蚀刻速率
公开(公告)号：US07541290B2
公开(公告)日：2009-06-02
申请号：US11683648
申请日：2007-03-08
申请人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinsky , Shailendra Mishra
发明人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinsky , Shailendra Mishra
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).
摘要翻译：形成集成电路器件的方法包括选择性地加宽邻近半导体晶片的外边缘延伸的掩模图案的部分的步骤。执行选择性拓宽掩模图案部分的这些步骤，使得当掩模图案用于支持下层（例如，绝缘层，抗反射涂层）的光刻图案化时，可以实现更均匀的中心至边缘临界尺寸（CD）等）。

2. 发明申请

US20080220609A1 Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing 有权
标题翻译：在光刻处理中补偿不均匀的中心到边缘蚀刻速率的半导体晶片上形成掩模图案的方法
公开(公告)号：US20080220609A1
公开(公告)日：2008-09-11
申请号：US11683648
申请日：2007-03-08
申请人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra
发明人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).
摘要翻译：形成集成电路器件的方法包括选择性地加宽邻近半导体晶片的外边缘延伸的掩模图案的部分的步骤。执行选择性拓宽掩模图案部分的这些步骤，使得当掩模图案用于支持下层（例如，绝缘层，抗反射涂层）的光刻图案化时，可以实现更均匀的中心至边缘临界尺寸（CD）等）。

3. 发明授权

US08697339B2 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08697339B2
公开(公告)日：2014-04-15
申请号：US13081377
申请日：2011-04-06
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.
摘要翻译：公开了制造半导体器件的方法。一个优选实施例是一种处理半导体器件的方法。该方法包括提供具有设置在其上的待图案化材料层的工件。在工件的材料层上形成掩模材料。掩模材料包括下部和设置在下部上的上部。用第一图案对掩模材料的上部进行图案化。聚合物材料设置在掩蔽材料上方。掩模材料和聚合物层用于对工件的材料层进行图案化。

4. 发明申请

US20080286698A1 Semiconductor device manufacturing methods 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20080286698A1
公开(公告)日：2008-11-20
申请号：US11804528
申请日：2007-05-18
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
IPC分类号： H01L21/02 , G03C5/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.
摘要翻译：公开了制造半导体器件的方法。一个优选实施例是一种处理半导体器件的方法。该方法包括提供具有设置在其上的待图案化材料层的工件。在工件的材料层上形成掩模材料。掩模材料包括下部和设置在下部上的上部。用第一图案对掩模材料的上部进行图案化。引入另外的物质，掩模材料的下部被图案化。掩模材料和附加物质用于对工件的材料层进行图案化。

5. 发明申请

US20110183266A1 Semiconductor Device Manufacturing Methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20110183266A1
公开(公告)日：2011-07-28
申请号：US13081377
申请日：2011-04-06
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.
摘要翻译：公开了制造半导体器件的方法。一个优选实施例是一种处理半导体器件的方法。该方法包括提供具有设置在其上的待图案化材料层的工件。在工件的材料层上形成掩模材料。掩模材料包括下部和设置在下部上的上部。用第一图案对掩模材料的上部进行图案化。聚合物材料设置在掩蔽材料上方。掩模材料和聚合物层用于对工件的材料层进行图案化。

6. 发明授权

US07759235B2 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07759235B2
公开(公告)日：2010-07-20
申请号：US11810810
申请日：2007-06-07
申请人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
发明人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
IPC分类号： H01L21/3205
CPC分类号： H01L27/11 , H01L27/0207
摘要： Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
摘要翻译：公开了制造半导体器件的方法。在优选实施例中，处理半导体器件的方法包括提供工件，所述工件包括待设置在其上的图案的材料层。在材料层上形成硬掩模。使用第一蚀刻工艺在硬掩模和材料层的上部形成第一图案。使用第二蚀刻工艺在硬掩模和材料层的上部形成第二图案，第二图案不同于第一图案。第一图案和第二图案使用第三蚀刻工艺形成在材料层的下部，并使用硬掩模作为掩模。

7. 发明申请

US20080305623A1 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20080305623A1
公开(公告)日：2008-12-11
申请号：US11810810
申请日：2007-06-07
申请人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
发明人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
IPC分类号： H01L21/8244
CPC分类号： H01L27/11 , H01L27/0207
摘要： Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
摘要翻译：公开了制造半导体器件的方法。在优选实施例中，处理半导体器件的方法包括提供工件，所述工件包括待设置在其上的图案的材料层。在材料层上形成硬掩模。使用第一蚀刻工艺在硬掩模和材料层的上部形成第一图案。使用第二蚀刻工艺在硬掩模和材料层的上部形成第二图案，第二图案不同于第一图案。第一图案和第二图案使用第三蚀刻工艺形成在材料层的下部，并使用硬掩模作为掩模。

8. 发明授权

US06328041B1 Universal cleaning wafer for a plasma chamber 失效
标题翻译：用于等离子体室的通用清洁晶片
公开(公告)号：US06328041B1
公开(公告)日：2001-12-11
申请号：US09156881
申请日：1998-09-18
申请人： Jeffrey J. Brown , Christopher N. Collins , Wilson Tong Lee , George A. Kaplita , Stefan Schmitz , Len Yuan Tsou
发明人： Jeffrey J. Brown , Christopher N. Collins , Wilson Tong Lee , George A. Kaplita , Stefan Schmitz , Len Yuan Tsou
IPC分类号： B08B704
CPC分类号： H01J37/32862 , C23C16/4405 , Y10S134/902 , Y10S156/916
摘要： A cleaning wafer is used during the vaporization of particulate deposits that were previously deposited on the walls of a plasma chamber. The cleaning wafer includes a first dielectric layer, a conducting layer and a second dielectric layer covering the conducting layer.
摘要翻译：在先前沉积在等离子体室的壁上的颗粒沉积物的蒸发期间使用清洁晶片。清洁晶片包括第一介电层，导电层和覆盖导电层的第二介电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式