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1. 发明申请

US20080305623A1 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20080305623A1
公开(公告)日：2008-12-11
申请号：US11810810
申请日：2007-06-07
申请人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
发明人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
IPC分类号： H01L21/8244
CPC分类号： H01L27/11 , H01L27/0207
摘要： Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
摘要翻译：公开了制造半导体器件的方法。在优选实施例中，处理半导体器件的方法包括提供工件，所述工件包括待设置在其上的图案的材料层。在材料层上形成硬掩模。使用第一蚀刻工艺在硬掩模和材料层的上部形成第一图案。使用第二蚀刻工艺在硬掩模和材料层的上部形成第二图案，第二图案不同于第一图案。第一图案和第二图案使用第三蚀刻工艺形成在材料层的下部，并使用硬掩模作为掩模。

2. 发明授权

US07759235B2 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07759235B2
公开(公告)日：2010-07-20
申请号：US11810810
申请日：2007-06-07
申请人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
发明人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
IPC分类号： H01L21/3205
CPC分类号： H01L27/11 , H01L27/0207
摘要： Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
摘要翻译：公开了制造半导体器件的方法。在优选实施例中，处理半导体器件的方法包括提供工件，所述工件包括待设置在其上的图案的材料层。在材料层上形成硬掩模。使用第一蚀刻工艺在硬掩模和材料层的上部形成第一图案。使用第二蚀刻工艺在硬掩模和材料层的上部形成第二图案，第二图案不同于第一图案。第一图案和第二图案使用第三蚀刻工艺形成在材料层的下部，并使用硬掩模作为掩模。

3. 发明授权

US08039203B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08039203B2
公开(公告)日：2011-10-18
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

4. 发明申请

US20090081563A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090081563A1
公开(公告)日：2009-03-26
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： G03F1/14 , G03F7/26
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

5. 发明授权

US08507346B2 Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer 有权
标题翻译：形成具有切割孔以暴露硬掩模层的一部分的半导体器件的方法
公开(公告)号：US08507346B2
公开(公告)日：2013-08-13
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/338 , H01L21/3205 , H01L21/4763 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

6. 发明申请

US20090181330A1 METHODS FOR FORMING A COMPOSITE PATTERN INCLUDING PRINTED RESOLUTION ASSIST FEATURES 有权
标题翻译：用于形成复合图案的方法，包括印刷分辨率辅助特征
公开(公告)号：US20090181330A1
公开(公告)日：2009-07-16
申请号：US12013627
申请日：2008-01-14
申请人： Allen H. Gabor , Scott D. Halle , Helen Wang
发明人： Allen H. Gabor , Scott D. Halle , Helen Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/0337 , G03F7/70433 , G03F7/70466
摘要： An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.
摘要翻译：在基板上形成图案化复合图案的底层。复合图案被分解为第一图案和第二图案，每个图案具有比复合图案更低的复杂度。硬掩模层直接形成在下层上。将第一光致抗蚀剂施加在硬掩模层上并用第一图案进行光刻图案化，其通过第一蚀刻转移到硬掩模层中。在硬掩模层上施加第二光致抗蚀剂。用第二图案对第二光致抗蚀剂进行图案化以暴露下层的部分。使用包含第一图案的第二光致抗蚀剂和硬掩模层来蚀刻下层的暴露部分，使得复合图案被转移到下层中。

7. 发明申请

US20120126294A1 WAFER FILL PATTERNS AND USES 有权
标题翻译： WAFER FILL PATTERNS和用途
公开(公告)号：US20120126294A1
公开(公告)日：2012-05-24
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L29/78 , H01L21/28 , H01L29/06 , H01L21/302
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

8. 发明授权

US08158334B2 Methods for forming a composite pattern including printed resolution assist features 有权
标题翻译：用于形成包括印刷分辨率辅助特征的复合图案的方法
公开(公告)号：US08158334B2
公开(公告)日：2012-04-17
申请号：US12013627
申请日：2008-01-14
申请人： Allen H. Gabor , Scott D. Halle , Helen Wang
发明人： Allen H. Gabor , Scott D. Halle , Helen Wang
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , G03F7/70433 , G03F7/70466
摘要： An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.
摘要翻译：在基板上形成图案化复合图案的底层。复合图案被分解为第一图案和第二图案，每个图案具有比复合图案更低的复杂度。硬掩模层直接形成在下层上。将第一光致抗蚀剂施加在硬掩模层上并用第一图案进行光刻图案化，其通过第一蚀刻转移到硬掩模层中。在硬掩模层上施加第二光致抗蚀剂。用第二图案对第二光致抗蚀剂进行图案化以暴露下层的部分。使用包含第一图案的第二光致抗蚀剂和硬掩模层来蚀刻下层的暴露部分，使得复合图案被转移到下层中。

9. 发明授权

US07993815B2 Line ends forming 有权
标题翻译：线端成型
公开(公告)号：US07993815B2
公开(公告)日：2011-08-09
申请号：US11853353
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L21/8229
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，该方法包括通过空间形成与第一器件元件分离的第一器件元件和第二器件元件; 以及形成从所述第一装置元件延伸的第一线，所述第一线包括在所述空间上并与所述第一装置元件间隔开的球形线端，以及从所述第二装置元件延伸的第二线，所述第二线包括球根线端并且与第二设备元件分开。

10. 发明授权

US06649531B2 Process for forming a damascene structure 有权
标题翻译：形成镶嵌结构的方法
公开(公告)号：US06649531B2
公开(公告)日：2003-11-18
申请号：US09994340
申请日：2001-11-26
申请人： William J. Cote , Timothy J. Dalton , Prakash Chimanlal Dev , Daniel C. Edelstein , Scott D. Halle , Gill Yong Lee , Arpan P. Mahorowala
发明人： William J. Cote , Timothy J. Dalton , Prakash Chimanlal Dev , Daniel C. Edelstein , Scott D. Halle , Gill Yong Lee , Arpan P. Mahorowala
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31633
摘要： A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.
摘要翻译：用于形成镶嵌结构的方法包括将包括第一介电层和第二介电层的双层沉积到基板上，其中第一层具有高于第二层的介电常数，并且其中第二层选自低k 包含Si，C，O和H的介电材料。使用高选择性各向异性反应离子蚀刻，将多步镶嵌结构图案化成电介质双层。使用等离子体灰化处理从基板去除光致抗蚀剂，聚合物和后蚀刻残留物，而不损坏下面的介电层。

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