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1. 发明授权

US08987813B2 High voltage metal-oxide-semiconductor transistor device 有权
标题翻译：高压金属氧化物半导体晶体管器件
公开(公告)号：US08987813B2
公开(公告)日：2015-03-24
申请号：US13571366
申请日：2012-08-10
申请人： Chiu-Te Lee , Ke-Feng Lin , Chih-Chien Chang , Wei-Lin Chen , Chih-Chung Wang
发明人： Chiu-Te Lee , Ke-Feng Lin , Chih-Chien Chang , Wei-Lin Chen , Chih-Chung Wang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/08
CPC分类号： H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/4236 , H01L29/42376 , H01L29/66704 , H01L29/7825
摘要： A high voltage metal-oxide-semiconductor transistor device includes a substrate, at least an isolation structure formed in the substrate, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective sides of the gate. The isolation structure further includes a recess. The gate includes a first gate portion formed on a surface of the substrate and a second gate portion downwardly extending from the first gate portion and formed in the recess.
摘要翻译：高压金属氧化物半导体晶体管器件包括至少形成在衬底中的隔离结构的衬底，形成在衬底上的栅极，以及形成在栅极各侧的衬底中的源极区和漏极区。隔离结构还包括凹部。栅极包括形成在基板的表面上的第一栅极部分和从第一栅极部分向下延伸并形成在凹部中的第二栅极部分。

2. 发明申请

US20130277742A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130277742A1
公开(公告)日：2013-10-24
申请号：US13454149
申请日：2012-04-24
申请人： Chiu-Te Lee , Ke-Feng Lin , Shu-Wen Lin , Kun-Huang Yu , Chih-Chung Wang , Te-Yuan Wu
发明人： Chiu-Te Lee , Ke-Feng Lin , Shu-Wen Lin , Kun-Huang Yu , Chih-Chung Wang , Te-Yuan Wu
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/7816
摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.
摘要翻译：半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。

3. 发明授权

US08852990B2 Method of fabricating solar cell 有权
标题翻译：制造太阳能电池的方法
公开(公告)号：US08852990B2
公开(公告)日：2014-10-07
申请号：US13589179
申请日：2012-08-20
申请人： Wei-Lin Chen , Chih-Chung Wang , Chiu-Te Lee , Ke-Feng Lin
发明人： Wei-Lin Chen , Chih-Chung Wang , Chiu-Te Lee , Ke-Feng Lin
IPC分类号： H01L31/18 , H01L31/0224 , H01L31/0236
CPC分类号： H01L31/18 , H01L31/02168 , H01L31/022425 , H01L31/02363 , H01L31/02366 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a solar cell includes the following steps. At first, a substrate including a doped layer is provided. Subsequently, a patterned material layer partially overlapping the doped layer is formed on the substrate, and a first metal layer is conformally formed on the patterned material layer and the doped layer. Furthermore, a patterned mask layer totally overlapping the patterned material layer is formed on the first metal layer, and a second metal layer is formed on the doped layer not overlapped by the patterned material layer. Then, the patterned mask layer, the first metal layer between the patterned mask layer and the patterned material layer and a part of the patterned material layer are removed.
摘要翻译：制造太阳能电池的方法包括以下步骤。首先，提供包括掺杂层的衬底。随后，在衬底上形成部分地与掺杂层重叠的图案化材料层，并且第一金属层保形地形成在图案化材料层和掺杂层上。此外，在第一金属层上形成与图案化材料层完全重叠的图案化掩模层，并且在不与图案化材料层重叠的掺杂层上形成第二金属层。然后，去除图案化掩模层，图案化掩模层和图案化材料层之间的第一金属层和图案化材料层的一部分。

4. 发明申请

US20100055912A1 SEMICONDUCTOR FABRICATING PROCESS 有权
公开(公告)号：US20100055912A1
公开(公告)日：2010-03-04
申请号：US12202548
申请日：2008-09-02
申请人： Chiu-Te Lee
发明人： Chiu-Te Lee
IPC分类号： H01L21/311
CPC分类号： H01L27/11526 , H01L27/11534
摘要： A semiconductor fabricating process is provided. First, a substrate is provided. The substrate has thereon a stacked structure and a mask layer disposed on the stacked structure. Thereafter, an oxide layer is formed on a surface of the mask layer and a surface of at least a portion of the stacked structure. Afterwards, a first spacer is formed on a sidewall of the stacked structure. Then, a second spacer is formed on a sidewall of the first spacer. Further, a first etching process is performed to remove the oxide layer on the surface of the mask layer. Thereafter, a second etching process is performed to simultaneously remove the mask layer and the second spacer.
摘要翻译：提供半导体制造工艺。首先，提供基板。基板上具有堆叠结构和设置在堆叠结构上的掩模层。此后，在掩模层的表面和堆叠结构的至少一部分的表面上形成氧化物层。之后，在堆叠结构的侧壁上形成第一间隔物。然后，在第一间隔物的侧壁上形成第二间隔物。此外，进行第一蚀刻工艺以去除掩模层表面上的氧化物层。此后，进行第二蚀刻处理以同时去除掩模层和第二间隔物。

5. 发明申请

US20070052053A1 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR AND FABRICATING METHOD THEREOF 有权
标题翻译：补充金属氧化物半导体图像传感器及其制造方法
公开(公告)号：US20070052053A1
公开(公告)日：2007-03-08
申请号：US11162118
申请日：2005-08-29
申请人： Chiu-Te Lee
发明人： Chiu-Te Lee
IPC分类号： H01L31/06
CPC分类号： H01L27/14683 , H01L27/14623 , H01L27/14625 , H01L27/14629
摘要： A CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging element is described. The light-receiving element and the transistor are disposed respectively inside the light sensing region and the transistor region. The first dielectric layer is disposed on the substrate, covering the transistor and the light-receiving element. The reflective layer is disposed on the first dielectric layer inside the light sensing region. The second dielectric layer is disposed on the first dielectric layer outside of the reflective layer. The material layer is disposed on the first dielectric layer inside of the reflective layer. The optical filter is disposed on the transparent material layer and the converging element is disposed on the optical filter inside the light sensing region.
摘要翻译：一种CMOS图像传感器，包括光接收元件，至少一个晶体管，第一介电层，反射层，第二介电层，保护层，材料层，透明材料层，滤光器和会聚描述元素。光接收元件和晶体管分别设置在光感测区域和晶体管区域内。第一电介质层设置在衬底上，覆盖晶体管和光接收元件。反射层设置在光感测区域内的第一介质层上。第二电介质层设置在反射层外侧的第一电介质层上。材料层设置在反射层内部的第一介电层上。滤光器设置在透明材料层上，并且会聚元件设置在光感测区域内的滤光器上。

6. 发明申请

US20050110148A1 FUSE STUCTURE 有权
标题翻译：保险丝座
公开(公告)号：US20050110148A1
公开(公告)日：2005-05-26
申请号：US10904081
申请日：2004-10-22
申请人： Chiu-Te Lee , Te-Yuan Wu
发明人： Chiu-Te Lee , Te-Yuan Wu
IPC分类号： H01L21/60 , H01L23/525 , H01L29/40
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.
摘要翻译：公开了一种金属层结构。金属层结构包括基板，在基板的表面上的第一介电层以及第一介电层上的至少一个第一导体和至少一个第二导体。第二导体具有至少一个薄部分。

7. 发明授权

US06864124B2 Method of forming a fuse 有权
标题翻译：形成保险丝的方法
公开(公告)号：US06864124B2
公开(公告)日：2005-03-08
申请号：US10064052
申请日：2002-06-05
申请人： Chiu-Te Lee , Te-Yuan Wu
发明人： Chiu-Te Lee , Te-Yuan Wu
IPC分类号： H01L21/60 , H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12 kÅ and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5 kÅ. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.
摘要翻译：半导体衬底的表面，其被限定有至少一个熔丝区域和至少一个焊盘区域。在半导体衬底的表面上依次形成厚度为12kA的导电层和保护层。然后，将保护层的部分和熔丝区域中的导电层的部分进行蚀刻，以使保险丝区域中的剩余导电层的厚度为约5k。最后，在半导体衬底的表面上形成电介质层，并且蚀刻第一电介质层的部分和焊盘区域中的保护层的部分，直到到达导电层的顶表面。

8. 发明授权

US06620721B1 Method of forming a self-aligning pad 有权
标题翻译：形成自对准垫的方法
公开(公告)号：US06620721B1
公开(公告)日：2003-09-16
申请号：US10064039
申请日：2002-06-04
申请人： Chiu-Te Lee
发明人： Chiu-Te Lee
IPC分类号： H11L2144
CPC分类号： H01L21/76858 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A method of forming a bonding pad on a substrate is provided. A first dielectric layer and at least one first conductive layer are included on the substrate. A second conductive layer is formed on the surface of the substrate. Then a heat treatment process is performed to form a third conductive layer in the first and the second conductive layers and completely oxidize the remaining second conductive layer to form a second dielectric layer. Finally a third dielectric layer is formed and each dielectric layer on the first conductive layer is removed.
摘要翻译：提供了在基板上形成接合焊盘的方法。第一介电层和至少一个第一导电层包括在基板上。在基板的表面上形成第二导电层。然后进行热处理工艺以在第一和第二导电层中形成第三导电层，并完全氧化剩余的第二导电层以形成第二介电层。最后，形成第三电介质层，并且去除第一导电层上的每个电介质层。

9. 发明授权

US08766358B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08766358B2
公开(公告)日：2014-07-01
申请号：US13454149
申请日：2012-04-24
申请人： Chiu-Te Lee , Ke-Feng Lin , Shu-Wen Lin , Kun-Huang Yu , Chih-Chung Wang , Te-Yuan Wu
发明人： Chiu-Te Lee , Ke-Feng Lin , Shu-Wen Lin , Kun-Huang Yu , Chih-Chung Wang , Te-Yuan Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/7816
摘要： A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.
摘要翻译：半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。

10. 发明申请

US20130062701A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130062701A1
公开(公告)日：2013-03-14
申请号：US13227487
申请日：2011-09-08
申请人： Chiu-Te Lee , Chun-Mao Chiou , You-Di Jhang
发明人： Chiu-Te Lee , Chun-Mao Chiou , You-Di Jhang
IPC分类号： H01L27/092 , H01L21/768 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76843 , H01L21/76865 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L23/485 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one sacrificial gate structure is formed on the substrate, at least one diffusion region is formed in the substrate at each of two sides of the sacrificial gate structure, and a first inter-layer dielectric layer is formed to cover the diffusion region. A gate recess is then formed in the sacrificial gate structure. A first diffusion contact hole is then formed in the first inter-layer dielectric layer and at least partially exposes the diffusion region. A metal layer is subsequently formed in the gate recess and the first diffusion contact hole.
摘要翻译：半导体器件的制造方法包括以下步骤。首先，提供基板。在基板上形成至少一个牺牲栅极结构，在牺牲栅极结构的两侧的每一侧的基板中形成至少一个扩散区，并且形成第一层间电介质层以覆盖扩散区。然后在牺牲栅极结构中形成栅极凹部。然后在第一层间电介质层中形成第一扩散接触孔，并且至少部分地暴露扩散区域。随后在栅极凹部和第一扩散接触孔中形成金属层。

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