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1. 发明申请

US20130062701A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130062701A1
公开(公告)日：2013-03-14
申请号：US13227487
申请日：2011-09-08
申请人： Chiu-Te Lee , Chun-Mao Chiou , You-Di Jhang
发明人： Chiu-Te Lee , Chun-Mao Chiou , You-Di Jhang
IPC分类号： H01L27/092 , H01L21/768 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76843 , H01L21/76865 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L23/485 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one sacrificial gate structure is formed on the substrate, at least one diffusion region is formed in the substrate at each of two sides of the sacrificial gate structure, and a first inter-layer dielectric layer is formed to cover the diffusion region. A gate recess is then formed in the sacrificial gate structure. A first diffusion contact hole is then formed in the first inter-layer dielectric layer and at least partially exposes the diffusion region. A metal layer is subsequently formed in the gate recess and the first diffusion contact hole.
摘要翻译：半导体器件的制造方法包括以下步骤。首先，提供基板。在基板上形成至少一个牺牲栅极结构，在牺牲栅极结构的两侧的每一侧的基板中形成至少一个扩散区，并且形成第一层间电介质层以覆盖扩散区。然后在牺牲栅极结构中形成栅极凹部。然后在第一层间电介质层中形成第一扩散接触孔，并且至少部分地暴露扩散区域。随后在栅极凹部和第一扩散接触孔中形成金属层。

2. 发明授权

US08461049B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08461049B2
公开(公告)日：2013-06-11
申请号：US13270229
申请日：2011-10-11
申请人： Chu-Chun Chang , Chun-Mao Chiou , Chiu-Te Lee
发明人： Chu-Chun Chang , Chun-Mao Chiou , Chiu-Te Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545 , H01L29/7834 , H01L29/7843
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供其上具有栅极结构的衬底; 在所述基板的表面和所述栅极结构的侧壁上形成第一盖层; 在所述第一盖层上形成第二盖层; 在所述第二盖层上形成第三盖层; 执行蚀刻工艺以部分地去除第三盖层，第二盖层和第一盖层，以在栅极结构的侧壁上形成第一间隔物和第二间隔物; 以及在所述衬底上形成接触蚀刻停止层（CESL）以覆盖所述第二间隔物，其中所述第三覆盖层和所述CESL包括相同的沉积条件。

3. 发明申请

US20130087837A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130087837A1
公开(公告)日：2013-04-11
申请号：US13270229
申请日：2011-10-11
申请人： Chu-Chun Chang , Chun-Mao Chiou , Chiu-Te Lee
发明人： Chu-Chun Chang , Chun-Mao Chiou , Chiu-Te Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545 , H01L29/7834 , H01L29/7843
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供其上具有栅极结构的衬底; 在所述基板的表面和所述栅极结构的侧壁上形成第一盖层; 在所述第一盖层上形成第二盖层; 在所述第二盖层上形成第三盖层; 执行蚀刻工艺以部分地去除第三盖层，第二盖层和第一盖层，以在栅极结构的侧壁上形成第一间隔物和第二间隔物; 以及在所述衬底上形成接触蚀刻停止层（CESL）以覆盖所述第二间隔物，其中所述第三覆盖层和所述CESL包括相同的沉积条件。

4. 发明申请

US20130270613A1 METHOD OF TRIMMING SPACERS AND SEMICONDUCTOR STRUCTURE THEREOF 有权
标题翻译：研磨间隔物及其半导体结构的方法
公开(公告)号：US20130270613A1
公开(公告)日：2013-10-17
申请号：US13447311
申请日：2012-04-16
申请人： Shyan-Liang Chou , Tsung-Min Kuo , Po-Wen Su , Chun-Mao Chiou , Feng-Mou Chen
发明人： Shyan-Liang Chou , Tsung-Min Kuo , Po-Wen Su , Chun-Mao Chiou , Feng-Mou Chen
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843
摘要： A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.
摘要翻译：修整间隔物的方法包括在形成最外层间隔物时蚀刻氧化硅间隔物，使得接触栅电极的硅氮化物间隔物露出一个区域。然后可以通过磷酸将部分地除去硅氮化硅间隔物的暴露面积。在半导体工艺结束时，硅碳氮化物间隔物的顶表面的至少一部分将低于栅电极的顶表面。

5. 发明授权

US08975673B2 Method of trimming spacers and semiconductor structure thereof 有权
标题翻译：修剪间隔物及其半导体结构的方法
公开(公告)号：US08975673B2
公开(公告)日：2015-03-10
申请号：US13447311
申请日：2012-04-16
申请人： Shyan-Liang Chou , Tsung-Min Kuo , Po-Wen Su , Chun-Mao Chiou , Feng-Mou Chen
发明人： Shyan-Liang Chou , Tsung-Min Kuo , Po-Wen Su , Chun-Mao Chiou , Feng-Mou Chen
IPC分类号： H01L29/76 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843
摘要： A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.
摘要翻译：修整间隔物的方法包括在形成最外层间隔物时蚀刻氧化硅间隔物，使得接触栅电极的硅氮化物间隔物露出一个区域。然后可以通过磷酸将部分地除去硅氮化硅间隔物的暴露面积。在半导体工艺结束时，硅碳氮化物间隔物的顶表面的至少一部分将低于栅电极的顶表面。

6. 发明授权

US08524556B1 Resistor and manufacturing method thereof 有权
标题翻译：电阻及其制造方法
公开(公告)号：US08524556B1
公开(公告)日：2013-09-03
申请号：US13419437
申请日：2012-03-14
申请人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
发明人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629
摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.
摘要翻译：一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

7. 发明授权

US08673755B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08673755B2
公开(公告)日：2014-03-18
申请号：US13282475
申请日：2011-10-27
申请人： Chu-Chun Chang , Kuang-Hung Huang , Chun-Mao Chiou , Yi-Chung Sheng
发明人： Chu-Chun Chang , Kuang-Hung Huang , Chun-Mao Chiou , Yi-Chung Sheng
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device, a second semiconductor device, and a first insulating layer covering the first semiconductor device and the second semiconductor device formed thereon, performing an etching process to remove a portion of the first insulating layer to expose a portion of the first semiconductor device and the second semiconductor device, forming a second insulating layer covering the first semiconductor device and the second semiconductor device, performing a first planarization process to remove a portion of the second insulating layer, forming a first gate trench and a second gate trench respectively in the first semiconductor device and the second semiconductor device, and forming a first metal gate and a second metal gate respectively in the first gate trench and the second gate trench.
摘要翻译：具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件，第二半导体器件以及覆盖形成在其上的第一半导体器件和第二半导体器件的第一绝缘层的衬底，进行蚀刻处理以去除所述第一绝缘层的一部分暴露所述第一半导体器件和所述第二半导体器件的一部分，形成覆盖所述第一半导体器件和所述第二半导体器件的第二绝缘层，执行第一平坦化处理以去除所述第二绝缘层的一部分分别在所述第一半导体器件和所述第二半导体器件中分别形成第一栅极沟槽和第二栅极沟槽，以及分别在所述第一栅极沟槽和所述第二栅极沟槽中形成第一金属栅极和第二金属栅极。

8. 发明申请

US20130241002A1 RESISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电阻及其制造方法
公开(公告)号：US20130241002A1
公开(公告)日：2013-09-19
申请号：US13419437
申请日：2012-03-14
申请人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
发明人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0629
摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.
摘要翻译：一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

9. 发明授权

US08518823B2 Through silicon via and method of forming the same 有权
标题翻译：通过硅通孔及其形成方法
公开(公告)号：US08518823B2
公开(公告)日：2013-08-27
申请号：US13335948
申请日：2011-12-23
申请人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
发明人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.
摘要翻译：本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。绝缘层设置在通孔开口的表面上。阻挡层设置在绝缘层的表面上。导电电极设置在缓冲层的表面上并填充通孔。缓冲层进一步覆盖在第二表面侧的导电电极的表面。本发明还公开了一种形成TSV的方法。

10. 发明申请

US20130161796A1 THROUGH SILICON VIA AND METHOD OF FORMING THE SAME 有权
标题翻译：通过硅和其形成方法
公开(公告)号：US20130161796A1
公开(公告)日：2013-06-27
申请号：US13335948
申请日：2011-12-23
申请人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
发明人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.
摘要翻译：本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。绝缘层设置在通孔开口的表面上。阻挡层设置在绝缘层的表面上。导电电极设置在缓冲层的表面上并填充通孔。缓冲层进一步覆盖在第二表面侧的导电电极的表面。本发明还公开了一种形成TSV的方法。

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