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1. 发明授权

US06528349B1 Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability 失效
标题翻译：具有晶圆级可靠性和功能可测性的单片制造兼容晶圆级封装
公开(公告)号：US06528349B1
公开(公告)日：2003-03-04
申请号：US09697031
申请日：2000-10-26
申请人： Chirag S. Patel , Kevin Martin , James D. Meindl
发明人： Chirag S. Patel , Kevin Martin , James D. Meindl
IPC分类号： H01L2144
CPC分类号： H01L23/3114 , H01L24/02 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/0231 , H01L2224/0233 , H01L2224/0235 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/1147 , H01L2224/13022 , H01L2224/13116 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2224/13099
摘要： Compliant wafer level packages 10 and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package 10 having a compliant layer 14 and a compliant interconnect 30 passing therein. The compliant interconnects 30 being provided so that electrical and mechanical connections may be supported across the compliant layer 14, and constructed so that stresses related to relative motion between electrical components is accommodated. A method of providing a substrate 10 having a compliant layer 14, the compliant layer 14 having a via 20 that exposes a die pad 12 on the substrate 10. Fabricating a compliant interconnect 30 so that the compliant interconnect 30 contacts the die pad 12. The compliant interconnect 30 constructed so that electrical and mechanical connections may be supported through the compliant layer 14.
摘要翻译：符合标准的晶圆级封装10及其整体制造方法。具有柔性层14和通过其中的顺应性互连30的单片制造的柔性晶片级封装10。柔性互连件30被设置成使得电气和机械连接可跨越顺应性层14被支撑，并被构造成使得与电气部件之间的相对运动相关的应力被容纳。一种提供具有柔性层14的衬底10的方法，柔性层14具有通孔20，该通孔20使衬底10上的管芯焊盘12暴露出来。制造柔性互连件30，使柔性互连件30与管芯焊盘12接触。被构造成使得电气和机械连接可以通过柔性层14被支撑。

2. 发明授权

US07132736B2 Devices having compliant wafer-level packages with pillars and methods of fabrication 失效
公开(公告)号：US07132736B2
公开(公告)日：2006-11-07
申请号：US10285034
申请日：2002-10-31
申请人： Muhannad S. Bakir , James D. Meindl , Chirag S. Patel
发明人： Muhannad S. Bakir , James D. Meindl , Chirag S. Patel
IPC分类号： H01L29/40 , H01L23/02 , H01L23/48
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2224/13 , H01L2224/13011 , H01L2224/13099 , H01L2224/45144 , H01L2224/45147 , H01L2224/48644 , H01L2224/48647 , H01L2224/48844 , H01L2224/48847 , H01L2224/85444 , H01L2224/85447 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.

3. 发明授权

US07266267B2 Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof 有权
标题翻译：微流体，光学和电输入输出互连，其制造方法及其使用方法
公开(公告)号：US07266267B2
公开(公告)日：2007-09-04
申请号：US11261149
申请日：2005-10-28
申请人： Muhannad S. Bakir , James D. Meindl
发明人： Muhannad S. Bakir , James D. Meindl
IPC分类号： G02B6/26
CPC分类号： B81B7/0006 , B01J2219/0081 , B01L3/502715 , B01L2200/027 , B81B2201/058 , B81B2207/07 , G02B6/24
摘要： Input/output (I/O) interconnects, fluidic I/O interconnects, electrical, optical, and fluidic I/O interconnects, devices incorporating the I/O interconnects, systems incorporating the I/O interconnects, and methods of fabricating the I/O interconnects, devices, and systems, are described herein.
摘要翻译：输入/输出（I / O）互连，流体I / O互连，电气，光学和流体I / O互连，并入I / O互连的设备，并入I / O互连的系统，以及制造I / O互连，设备和系统。

4. 发明申请

US20070176248A1 HIGH DIELECTRIC CONSTANT INSULATORS AND ASSOCIATED FABRICATION METHODS 有权
标题翻译：高介电常数绝缘子及相关制造方法
公开(公告)号：US20070176248A1
公开(公告)日：2007-08-02
申请号：US11669086
申请日：2007-01-30
申请人： THOMAS K. GAYLORD , James D. Meindl
发明人： THOMAS K. GAYLORD , James D. Meindl
IPC分类号： H01L29/94
CPC分类号： H01L29/51 , H01L21/02142 , H01L21/02175 , H01L21/02197 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691
摘要： High-dielectric-constant (k) materials and electrical devices implementing the high-k materials are provided herein. According to some embodiments, an electrical device includes a substrate and a crystalline-oxide-containing composition. The crystalline-oxide-containing composition can be disposed on a surface of the substrate. Within the crystalline-oxide-containing composition, oxide anions can form at least one of a substantially linear orientation or a substantially planar orientation. A plurality of these substantially linear orientations of oxide anions or substantially planar orientations of oxide anions can be oriented substantially perpendicular or substantially normal to the surface of the substrate such that the oxide-containing composition has a dielectric constant greater than about 3.9 in a direction substantially normal to the surface of the substrate. Other embodiments are also claimed and described.
摘要翻译：本文提供了高介电常数（k）材料和实施高k材料的电气设备。根据一些实施例，电气装置包括基底和含结晶氧化物的组合物。含结晶氧化物的组合物可以设置在基材的表面上。在含结晶氧化物的组合物中，氧化物阴离子可以形成基本上线性取向或基本平面取向中的至少一个。氧化物阴离子的氧化物阴离子或基本上平面取向的多个这些基本上线性的取向可以被定向为基本上垂直于或基本上垂直于衬底的表面，使得含氧化物的组合物在基本上在基本上的方向上具有大于约3.9的介电常数垂直于基底的表面。还要求保护和描述其它实施例。

5. 发明授权

US07935459B2 Photo-masks and methods of fabricating surface-relief grating diffractive devices 有权
$Photo-masks and methods of fabricating surface-relief grating diffractive devices$
标题翻译：光掩模和制造表面浮雕光栅衍射装置的方法
公开(公告)号：US07935459B2
公开(公告)日：2011-05-03
申请号：US11767372
申请日：2007-06-22
申请人： Thomas K. Gaylord , Justin L. Stay , Jonathan S. Maikisch , James D. Meindl
发明人： Thomas K. Gaylord , Justin L. Stay , Jonathan S. Maikisch , James D. Meindl
IPC分类号： G03F1/00 , G02B5/18
CPC分类号： G02B5/1857 , G02B27/4238
摘要： Photo-masks for fabricating surface-relief grating diffractive devices and methods of fabricating surface-relief grating diffractive devices are described. The photo-mask can include refractive elements and/or diffractive elements contained in or on a body element. The photo-mask can be used to simultaneously produce multiple surface-relief grating diffractive devices in a recording material. The photo-mask enables the surface-relief grating diffractive devices to be produced in large quantities while significantly reducing the cost and labor required.
摘要翻译：描述了用于制造表面浮雕光栅衍射装置的照相掩模和制造表面浮雕光栅衍射装置的方法。光掩模可以包括包含在体元件中或其上的折射元件和/或衍射元件。光掩模可用于在记录材料中同时产生多个表面浮雕光栅衍射装置。光掩模使得能够大量地生产表面浮雕光栅衍射装置，同时显着降低所需的成本和劳动。

6. 发明授权

US07468558B2 Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof 有权
标题翻译：具有兼容的晶片级输入/输出互连和使用柱的封装的器件及其制造方法
公开(公告)号：US07468558B2
公开(公告)日：2008-12-23
申请号：US11416686
申请日：2006-05-03
申请人： Muhannad S. Bakir , Kevin P. Martin , James D. Meindl
发明人： Muhannad S. Bakir , Kevin P. Martin , James D. Meindl
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G01R31/2863 , G01R1/0491 , G02B6/12002 , G02B6/42 , G02B6/43 , G02B2006/12107 , H01L23/49811 , H01L2224/81141 , H01L2224/81193 , H05K3/303 , H05K3/326 , H05K2203/167 , Y02P70/613
摘要： Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.
摘要翻译：具有以下一个或多个的设备：公开了输入/输出（I / O）互连系统，光学I / O互连，电气I / O互连，射频I / O互连。代表性的I / O互连系统包括第一基板和第二基板。第一衬底包括从第一衬底垂直延伸的柔性柱。柔性支柱由第一材料构成。第二基板包括适于容纳柔性支柱的柔性插座。兼容插座由第二材料构成。

7. 发明授权

US07348786B2 Probe module for testing chips with electrical and optical input/output interconnects, methods of use, and methods of fabrication 失效
标题翻译：用于测试具有电和光输入/输出互连的芯片的探针模块，使用方法和制造方法
公开(公告)号：US07348786B2
公开(公告)日：2008-03-25
申请号：US11216645
申请日：2005-08-31
申请人： Hiren D. Thacker , Oluwafemi O. Ogunsola , James D. Meindl
发明人： Hiren D. Thacker , Oluwafemi O. Ogunsola , James D. Meindl
IPC分类号： G01R31/02 , G01R31/302 , G01R31/308
CPC分类号： G01R31/311 , G01R1/07314 , G01R31/2889 , G02B6/12 , G02B6/12004 , G02B6/4214
摘要： Probe modules, methods of use of probe modules, and methods of preparing probe modules, are disclosed. A representative embodiment of a probe module, among others, includes a redistribution substrate and a probe substrate interfaced with the redistribution substrate. The probe substrate is operative to test at least one signal of at least one optoelectronic device under test. The probe substrate is operative to interface with electrical and optical components.
摘要翻译：公开了探针模块，探针模块的使用方法和制备探针模块的方法。探针模块的代表性实施例等等包括与再分布衬底接口的再分布衬底和探针衬底。探针衬底可操作以测试至少一个被测光电器件的至少一个信号。探针基板可操作以与电气和光学部件相接合。

8. 发明授权

US06807352B2 Optical waveguides with embedded air-gap cladding layer and methods of fabrication thereof 有权
标题翻译：具有嵌入式气隙包覆层的光波导及其制造方法
公开(公告)号：US06807352B2
公开(公告)日：2004-10-19
申请号：US10074067
申请日：2002-02-11
申请人： Tony Mule′ , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Paul Kohl
发明人： Tony Mule′ , James D. Meindl , Thomas K. Gaylord , Elias N. Glytsis , Paul Kohl
IPC分类号： G02B610
CPC分类号： G02B6/136 , G02B6/10 , G02B6/1221 , G02B6/132 , G02B6/34 , G02B6/43 , G02B2006/12107
摘要： Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.
摘要翻译：公开了具有气隙包覆层的波导和制造具有气隙包覆层的波导的方法。代表性的波导包括具有接合波导芯的一部分的气隙包覆层的波导芯。另外，制造具有气隙包层的波导的代表性方法包括：提供具有设置在基板上的下包层的基板; 在所述下包层的一部分上设置波导芯; 在所述下包层和所述波导芯的至少一部分上设置牺牲层; 在下包层和牺牲层上设置外涂层; 以及去除所述牺牲层以在所述外涂层聚合物层内限定气隙包层并与所述波导芯的一部分接合。

9. 发明授权

US4285001A Monolithic distributed resistor-capacitor device and circuit utilizing polycrystalline semiconductor material 失效
标题翻译：使用多晶半导体材料的单片分布式电阻电容器件和电路
公开(公告)号：US4285001A
公开(公告)日：1981-08-18
申请号：US972738
申请日：1978-12-26
申请人： Levy Gerzberg , James D. Meindl
发明人： Levy Gerzberg , James D. Meindl
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/07 , H01L29/94 , H01L27/13
CPC分类号： H01L28/20 , H01L27/0755 , H01L27/0794 , H01L29/94
摘要： A distributed resistor-capacitor device which is highly reproducible with near ideal electrical characteristics including a substrate, an insulating layer on a major surface of the substrate, and a polycrystalline semiconductor material on the insulating layer. The polycrystalline layer is the resistor and cooperates with the substrate as the capacitor. Fabrication of the device is compatible with integrated circuit fabrication and can be used with field-effect and bipolar junction transistors.
摘要翻译：一种分布式电阻器电容器，其具有包括基板，基板主表面上的绝缘层和绝缘层上的多晶半导体材料的近似理想电特性的高度可再现性。多晶层是电阻器，并与基片作为电容器配合使用。该器件的制造与集成电路制造兼容，可用于场效应和双极结型晶体管。

10. 发明授权

US08563365B2 Air-gap C4 fluidic I/O interconnects and methods of fabricating same 有权
标题翻译：气隙C4流体I / O互连及其制造方法
公开(公告)号：US08563365B2
公开(公告)日：2013-10-22
申请号：US13416849
申请日：2012-03-09
申请人： Calvin Richard King, Jr. , Jesal Zevari , James D. Meindl , Muhannad S. Bakir
发明人： Calvin Richard King, Jr. , Jesal Zevari , James D. Meindl , Muhannad S. Bakir
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/48 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/03462 , H01L2224/0401 , H01L2224/05551 , H01L2224/0557 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/0603 , H01L2224/06051 , H01L2224/11462 , H01L2224/13011 , H01L2224/13025 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81203 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.
摘要翻译：本发明的示例性实施例提供了一种用于制造三维集成电路的芯片，该芯片包括晶片，一个或多个金属填充的电气通孔以及一个或多个中空的流体通孔。晶片可以包括第一表面和第二表面。一个或多个金属填充的电气通孔可以延伸穿过晶片。每个电通孔可以与靠近第一表面的电互连电连通，从而提供集成电路中的芯片之间的电通信。一个或多个中空的流体通孔可延伸穿过晶片。每个流体通道可以与流体互连流体连通，从而提供集成电路中的相邻芯片之间的流体连通。每个流体互连可以包括靠近第一表面的第一端，第二端和靠近第二端的盖，限定流体互连内的空气填充空间。

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