专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08692359B2 Through silicon via structure having protection ring 有权
标题翻译：通过具有保护环的硅通孔结构
公开(公告)号：US08692359B2
公开(公告)日：2014-04-08
申请号：US13309559
申请日：2011-12-02
申请人： Yung-Chang Lin , Chien-Li Kuo , Ming-Tse Lin , Sun-Chieh Chien
发明人： Yung-Chang Lin , Chien-Li Kuo , Ming-Tse Lin , Sun-Chieh Chien
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L21/76232 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.
摘要翻译：制造半导体器件的方法包括以下步骤。提供了具有面向第一面的第一面和第二面的半导体衬底。至少一个开口设置在第一侧限定的保护区域的半导体衬底中。在第一侧和第二侧上形成第一材料层，第一材料层部分地填充开口。随后，去除第一侧的第一材料层和保护区域外部的一部分。在第一侧和第二侧上形成第二材料层，并且第二材料层填充开口。然后，去除保护区域的第一侧和外侧的第二材料层的一部分。最后，剩余的第一材料层和第一侧的剩余的第二材料层被平坦化。

2. 发明申请

US20130140708A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130140708A1
公开(公告)日：2013-06-06
申请号：US13309559
申请日：2011-12-02
申请人： Yung-Chang Lin , Chien-Li Kuo , Ming-Tse Lin , Sun-Chieh Chien
发明人： Yung-Chang Lin , Chien-Li Kuo , Ming-Tse Lin , Sun-Chieh Chien
IPC分类号： H01L23/498 , H01L21/76
CPC分类号： H01L21/76898 , H01L21/76232 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.
摘要翻译：制造半导体器件的方法包括以下步骤。提供了具有面向第一面的第一面和第二面的半导体衬底。至少一个开口设置在第一侧限定的保护区域的半导体衬底中。在第一侧和第二侧上形成第一材料层，第一材料层部分地填充开口。随后，去除第一侧的第一材料层和保护区域外部的一部分。在第一侧和第二侧上形成第二材料层，并且第二材料层填充开口。然后，去除保护区域的第一侧和外侧的第二材料层的一部分。最后，剩余的第一材料层和第一侧的剩余的第二材料层被平坦化。

3. 发明授权

US08441134B2 Chip stacking structure 有权
标题翻译：芯片堆叠结构
公开(公告)号：US08441134B2
公开(公告)日：2013-05-14
申请号：US13228549
申请日：2011-09-09
申请人： Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
发明人： Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
IPC分类号： H01L23/52 , H01L23/48 , H01L27/146 , H01L27/148
CPC分类号： H01L23/12 , H01L21/563 , H01L25/0657 , H01L2225/06513 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
摘要翻译：芯片堆叠结构包括第一芯片和第二芯片。第一芯片包括具有形成在其上的第一组焊盘的表面，并且第二芯片包括具有形成在其上的第二组焊盘的表面。第二组垫被粘合到第一组垫上以限定沿相同方向延伸的多个毛细通道。芯片堆叠结构还包括在第一芯片和第二芯片之间的底部填充填充间隙。芯片堆叠结构能够在焊接过程中避免芯片变形和开裂。

4. 发明申请

US20130015504A1 TSV STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译： TSV结构及其形成方法
公开(公告)号：US20130015504A1
公开(公告)日：2013-01-17
申请号：US13179577
申请日：2011-07-11
申请人： Chien-Li Kuo , Chin-Sheng Yang , Ming-Tse Lin
发明人： Chien-Li Kuo , Chin-Sheng Yang , Ming-Tse Lin
IPC分类号： H01L23/48 , H01L29/06 , H01L21/768 , H01L29/772
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L27/0694 , H01L27/12 , H01L2224/02372 , H01L2224/03 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/13024 , H01L2924/1461 , H01L2924/00
摘要： A TSV structure includes a wafer including a first side and a second side, a through via connecting the first side and the second side, a through via dielectric layer covering the inner wall of the through via, a conductive layer which fills up the through via and consists of a single material to be a seamless TSV structure, a first dielectric layer covering the first side and surrounding the conductive layer as well as a second dielectric layer covering the second side and part of the through via dielectric layer but partially covered by the conductive layer.
摘要翻译： TSV结构包括包括第一侧和第二侧的晶片，连接第一侧和第二侧的通孔，覆盖通孔内壁的通孔电介质层，填充通孔的导电层并且由单一材料构成为无缝TSV结构，覆盖第一侧并且围绕导电层的第一介电层以及覆盖通孔电介质层的第二侧面和部分通孔电介质层的第二电介质层，但部分被导电层。

5. 发明授权

US08026573B2 Electrical fuse structure 有权
标题翻译：电熔丝结构
公开(公告)号：US08026573B2
公开(公告)日：2011-09-27
申请号：US12335510
申请日：2008-12-15
申请人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
发明人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.
摘要翻译：公开了电熔丝结构。电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。具体而言，压电应力层设置在熔丝元件的至少一部分上。

6. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

7. 发明授权

US09275933B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09275933B2
公开(公告)日：2016-03-01
申请号：US13526533
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L29/49 , H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L21/823475 , H01L23/481 , H01L29/0649 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

8. 发明申请

US20130334699A1 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130334699A1
公开(公告)日：2013-12-19
申请号：US13526546
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/0228 , H01L21/02282 , H01L21/28026 , H01L21/31111 , H01L21/76224 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76877 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181
摘要： A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.
摘要翻译：一种半导体器件包括具有正面和背面的衬底，设置在衬底上的ILD，设置在衬底背面上的覆盖层，穿透覆盖层，衬底和ILD的TSV，其中帽 TSV中的层侧壁突出超过基板侧壁具有预定距离的TSV，并且衬垫设置在衬底侧壁上，其中衬垫部分地与盖层重叠。

9. 发明申请

US20130334669A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130334669A1
公开(公告)日：2013-12-19
申请号：US13526533
申请日：2012-06-19
申请人： Chien-Li Kuo , Yung-Chang Lin
发明人： Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L21/823475 , H01L23/481 , H01L29/0649 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的层间电介质; 穿透底物和ILD的TSV。此外，在衬底中设置多个浅沟槽隔离（STI），并且屏蔽环设置在围绕STI上的TSV的ILD中。在形成TSV的过程中，接触环可以保护邻近部件免受金属污染。

10. 发明申请

US20090236583A1 Method of fabricating a phase change memory and phase change memory 有权
标题翻译：制造相变存储器和相变存储器的方法
公开(公告)号：US20090236583A1
公开(公告)日：2009-09-24
申请号：US12053623
申请日：2008-03-24
申请人： Chien-Li Kuo , Kuei-Sheng Wu , Yung-Chang Lin
发明人： Chien-Li Kuo , Kuei-Sheng Wu , Yung-Chang Lin
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0069 , G11C2013/008 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683 , Y10S438/90
摘要： The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated.
摘要翻译：本发明涉及相变存储器和相变存储器的制造方法。相变存储器包括设置在相变材料图案上的加热器结构，其中加热器结构呈锥形，底部接触相变材料图案。相变存储器的制造与逻辑器件的制造兼容，因此可以制造嵌入式相变存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式