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1. 发明申请

US20100141346A1 Phase-Locked Loop with Start-Up Circuit 有权
标题翻译：带启动电路的锁相环
公开(公告)号：US20100141346A1
公开(公告)日：2010-06-10
申请号：US12330952
申请日：2008-12-09
申请人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shuch Yuan
发明人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shuch Yuan
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/10 , H03L7/0995
摘要： A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.
摘要翻译：电路包括压控振荡器（VCO），其包括具有输入电压的电压输入节点; 和启动电路。启动电路包括第一电流路径和第二电流路径。第一电流路径具有第一电流并且被配置为使得第一电流响应于输入电压的降低而增加，并且响应于输入电压的增加而减小。第二电流路径具有第二电流并且被配置为使得第二电流响应于输入电压的降低而减小，并且响应于输入电压的增加而减小。 VCO还包括将第一电流的第一比例和第二电流的第二比例组合成组合电流的第三电流通路; 以及电流控制振荡器（CCO），其包括接收组合电流的输入并输出AC信号。

2. 发明授权

US09112507B2 Phase-locked loop start up circuit 有权
标题翻译：锁相环启动电路
公开(公告)号：US09112507B2
公开(公告)日：2015-08-18
申请号：US12719951
申请日：2010-03-09
申请人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai
发明人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai
IPC分类号： H03L7/00 , H03L7/06 , H03L3/00 , H03L7/10
CPC分类号： H03L3/00 , H03L7/101
摘要： A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.
摘要翻译：锁相环（PLL）电路包括具有用于接收控制电压和VCO输出的VCO输入的压控振荡器（VCO），VCO输入和VCO输出之间的反馈环路，以及启动电路具有启动电路输入和启动电路输出。启动电路输出耦合到VCO输入，启动电路输入耦合到VCO输出。启动电路在启动阶段在其起动电路输出端提供电压，在起动电路检测到预定数量的反馈脉冲之后终止该电压。

3. 发明授权

US07791420B2 Phase-locked loop with start-up circuit 有权
标题翻译：带启动电路的锁相环
公开(公告)号：US07791420B2
公开(公告)日：2010-09-07
申请号：US12330952
申请日：2008-12-09
申请人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shueh Yuan
发明人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shueh Yuan
IPC分类号： H03K3/03 , H03L7/099
CPC分类号： H03L7/10 , H03L7/0995
摘要： A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.
摘要翻译：电路包括压控振荡器（VCO），其包括具有输入电压的电压输入节点; 和启动电路。启动电路包括第一电流路径和第二电流路径。第一电流路径具有第一电流并且被配置为使得第一电流响应于输入电压的降低而增加，并且响应于输入电压的增加而减小。第二电流路径具有第二电流并且被配置为使得第二电流响应于输入电压的降低而减小，并且响应于输入电压的增加而减小。 VCO还包括将第一电流的第一比例和第二电流的第二比例组合成组合电流的第三电流通路; 以及电流控制振荡器（CCO），其包括接收组合电流的输入并输出AC信号。

4. 发明授权

US09148135B2 Real time automatic and background calibration at embedded duty cycle correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US09148135B2
公开(公告)日：2015-09-29
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： G06F1/00 , H03K5/156 , G06F1/08
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

5. 发明申请

US20130342252A1 Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US20130342252A1
公开(公告)日：2013-12-26
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

6. 发明授权

US08692602B2 Method and apparatus of digital control delay line 有权
标题翻译：数字控制延时线的方法和装置
公开(公告)号：US08692602B2
公开(公告)日：2014-04-08
申请号：US13600021
申请日：2012-08-30
申请人： Mao-Hsuan Chou
发明人： Mao-Hsuan Chou
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/135 , H03L7/0814
摘要： A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.
摘要翻译：数字控制延迟线（DCDL）包括产生延迟信号的信号门控延迟线，相位选择器，控制器，输入信号和输出信号。相位选择器包括将来自信号门控延迟线的延迟信号耦合到输出信号的逻辑门。防止信号传播到未使用的单元和逻辑门可以减少功耗。延迟信号通过的相位选择器中的逻辑门的数量是log2p，其中p是信号选通延迟线中的信号门控延迟单元的数量，p是2的幂。逻辑门数是（ log2 p）+1的整数部分，其中p是信号门控延迟单元的数量，p不是2的幂。

7. 发明申请

US20140028366A1 Method and Apparatus of Digital Control Delay Line 有权
标题翻译：数字控制延时线的方法与装置
公开(公告)号：US20140028366A1
公开(公告)日：2014-01-30
申请号：US13600021
申请日：2012-08-30
申请人： Mao-Hsuan Chou
发明人： Mao-Hsuan Chou
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/135 , H03L7/0814
摘要： A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.
摘要翻译：数字控制延迟线（DCDL）包括产生延迟信号的信号门控延迟线，相位选择器，控制器，输入信号和输出信号。相位选择器包括将来自信号门控延迟线的延迟信号耦合到输出信号的逻辑门。防止信号传播到未使用的单元和逻辑门可以减少功耗。延迟信号通过的相位选择器中的逻辑门的数量是log2p，其中p是信号选通延迟线中的信号门控延迟单元的数量，p是2的幂。逻辑门数是（ log2 p）+1的整数部分，其中p是信号门控延迟单元的数量，p不是2的幂。

8. 发明授权

US08519765B2 Method and apparatus for signal phase calibration 有权
标题翻译：用于信号相位校准的方法和装置
公开(公告)号：US08519765B2
公开(公告)日：2013-08-27
申请号：US13228508
申请日：2011-09-09
申请人： Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03H11/16
CPC分类号： H03K5/135 , H03B19/00 , H03L7/099
摘要： A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.
摘要翻译：用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。这些信号具有共同的频率并且相互偏移倍数的相位偏移。检测到第一信号的边缘。第一个信号是参考信号的多个相移版本之一。边缘是从第一逻辑值到第二逻辑值的转换。第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。基于比较的结果选择性地提供第一信号的反转。

9. 发明授权

US09503103B2 Phase locked loop with a frequency multiplier and method of configuring the phase locked loop 有权
标题翻译：具有倍频器的锁相环和配置锁相环的方法
公开(公告)号：US09503103B2
公开(公告)日：2016-11-22
申请号：US13569643
申请日：2012-08-08
申请人： Mao-Hsuan Chou
发明人： Mao-Hsuan Chou
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/197 , H03L7/23
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976 , H03L7/23
摘要： A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.
摘要翻译：锁相环（PLL）电路包括倍频器和分数N型PLL。倍频器的时钟输出电连接到分数N型PLL的时钟输入。 PLL的倍频器的环路带宽小于PLL的分数N型PLL的环路带宽。

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