专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080128765A1 MOSFET Device With Localized Stressor 审中-公开
标题翻译：具有局部应力的MOSFET器件
公开(公告)号：US20080128765A1
公开(公告)日：2008-06-05
申请号：US12016499
申请日：2008-01-18
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

2. 发明授权

US07335544B2 Method of making MOSFET device with localized stressor 有权
标题翻译：制造具有局部应力源的MOSFET器件的方法
公开(公告)号：US07335544B2
公开(公告)日：2008-02-26
申请号：US11012413
申请日：2004-12-15
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源极/漏极区的晶体管，在栅电极和源极/漏极区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

3. 发明授权

US07232730B2 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US07232730B2
公开(公告)日：2007-06-19
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善其相应的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

4. 发明申请

US20100048011A1 METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE 有权
标题翻译：图案化半导体器件金属栅的方法
公开(公告)号：US20100048011A1
公开(公告)日：2010-02-25
申请号：US12371672
申请日：2009-02-16
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28105 , H01L21/28123 , H01L21/28158 , H01L21/31111 , H01L21/32139 , H01L29/401
摘要： Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
摘要翻译：提供了包括高k栅极电介质的金属栅极结构的图案化方法。在一个实施方案中，可以使用可溶性硬掩模层来提供掩模元件以对金属栅极进行图案化。可溶性硬掩模层可以通过水或光致抗蚀剂显影剂从基底上去除。在一个实施例中，形成包括高k电介质的硬掩模。在另一个实施例中，保护层形成在光致抗蚀剂图案下面。保护层可以保护形成在衬底上的一个或多个层与光致抗蚀剂剥离工艺。

5. 发明授权

US07989321B2 Semiconductor device gate structure including a gettering layer 有权
标题翻译：包括吸气层的半导体器件栅极结构
公开(公告)号：US07989321B2
公开(公告)日：2011-08-02
申请号：US12257165
申请日：2008-10-23
申请人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
发明人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/322 , H01L21/32
CPC分类号： H01L21/28518 , H01L21/28185 , H01L21/3221 , H01L29/49 , H01L29/51 , H01L29/513
摘要： A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.
摘要翻译：提供了一种方法，其允许通过减小栅极结构中的界面层的厚度来维持期望的等效氧化物厚度（EOT）。在基板上形成界面层，在界面层上形成栅极电介质层，例如高k栅极电介质。在覆盖界面层的基板上形成吸气层。吸气层可用于从界面层吸收氧气，使得界面层厚度减少和/或限制生长。

6. 发明申请

US20100048010A1 SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER 有权
标题翻译：半导体器件门结构包括入门层
公开(公告)号：US20100048010A1
公开(公告)日：2010-02-25
申请号：US12257165
申请日：2008-10-23
申请人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
发明人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/28
CPC分类号： H01L21/28518 , H01L21/28185 , H01L21/3221 , H01L29/49 , H01L29/51 , H01L29/513
摘要： A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.
摘要翻译：提供了一种方法，其允许通过减小栅极结构中的界面层的厚度来维持期望的等效氧化物厚度（EOT）。在基板上形成界面层，在界面层上形成栅极电介质层，例如高k栅极电介质。在覆盖界面层的基板上形成吸气层。吸气层可用于从界面层吸收氧气，使得界面层厚度减少和/或限制生长。

7. 发明授权

US08679962B2 Integrated circuit metal gate structure and method of fabrication 有权
标题翻译：集成电路金属栅极结构及其制造方法
公开(公告)号：US08679962B2
公开(公告)日：2014-03-25
申请号：US12264822
申请日：2008-11-04
申请人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
发明人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.
摘要翻译：提供一种形成栅极结构的方法。该方法包括在栅极结构中提供金属层，金属层包括吸氧组合物。金属层从界面层吸收氧气，这可能会降低界面层的厚度。吸收的氧将金属层转化为金属氧化物，其可以用作栅极结构的栅极电介质。还提供了多层金属栅极结构，其包括吸氧过程金属层，含氧金属层和覆盖在高k栅极电介质上的多晶硅界面金属层。

8. 发明申请

US20100044806A1 INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION 有权
标题翻译：集成电路金属结构和制造方法
公开(公告)号：US20100044806A1
公开(公告)日：2010-02-25
申请号：US12264822
申请日：2008-11-04
申请人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
发明人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.
摘要翻译：提供一种形成栅极结构的方法。该方法包括在栅极结构中提供金属层，金属层包括吸氧组合物。金属层从界面层吸收氧气，这可能会降低界面层的厚度。吸收的氧将金属层转化为金属氧化物，其可以用作栅极结构的栅极电介质。还提供了多层金属栅极结构，其包括吸氧过程金属层，含氧金属层和覆盖在高k栅极电介质上的多晶硅界面金属层。

9. 发明授权

US08357617B2 Method of patterning a metal gate of semiconductor device 有权
公开(公告)号：US08357617B2
公开(公告)日：2013-01-22
申请号：US12371672
申请日：2009-02-16
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
IPC分类号： H01L21/302
CPC分类号： H01L21/28105 , H01L21/28123 , H01L21/28158 , H01L21/31111 , H01L21/32139 , H01L29/401
摘要： Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

10. 发明申请

US20080138983A1 Method of forming tensile stress films for NFET performance enhancement 审中-公开
标题翻译：形成用于NFET性能提高的拉伸应力膜的方法
公开(公告)号：US20080138983A1
公开(公告)日：2008-06-12
申请号：US11634303
申请日：2006-12-06
申请人： Hao-Ming Lien , Jim Cy Huang , Donald Y. Chao , Ling-Yen Yeh , Hun-Jan Tao
发明人： Hao-Ming Lien , Jim Cy Huang , Donald Y. Chao , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/2686 , H01L21/76825 , H01L21/76828 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming tensile stress films for NFET Performance enhancement, comprising the steps of: (a) providing a semiconductor substrate having a gate structure patterned thereon; (b) performing a deposition process to form a first dielectric film overlying the semiconductor substrate and covering the gate structure; (c) performing a curing process on the first dielectric film; (d) successively repeating the step (b) of deposition process and the step (c) of curing process at least once to form at least one second dielectric film on the first dielectric film until the total thickness of the first dielectric film and the at least one second dielectric film reaches a target thickness.
摘要翻译：一种形成用于NFET性能增强的拉伸应力膜的方法，包括以下步骤：（a）提供在其上图案化的栅极结构的半导体衬底; （b）进行沉积工艺以形成覆盖半导体衬底并覆盖栅极结构的第一电介质膜; （c）对所述第一电介质膜进行固化处理; （d）连续重复沉积处理步骤（b）和固化过程的步骤（c）至少一次，以在第一介电膜上形成至少一个第二电介质膜，直到第一介电膜和第至少一个第二介电膜达到目标厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式