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1. 发明授权

US06255023B1 Method of manufacturing binary phase shift mask 有权
标题翻译：制造二元相移掩模的方法
公开(公告)号：US06255023B1
公开(公告)日：2001-07-03
申请号：US09434046
申请日：1999-11-04
申请人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
发明人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
IPC分类号： G03F900
CPC分类号： G03F1/32
摘要： A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.
摘要翻译：一种制造二进制相移光掩模的方法。在透明基板上依次形成相移层和掩模层。图案化掩模层和相移层以形成多个第一开口和暴露透明基板的一部分的多个第二开口。图案化掩模层以在第一开口的边缘周围形成掩模材料层。所有第一开口占据大于预设最小面积的区域，而所有第二开口占据大于预设最小面积的区域。掩模层仅围绕第一开口，而相移层围绕第一和第二开口。

2. 发明授权

US09673280B2 Cobalt silicidation process for substrates comprised with a silicon-germanium layer 有权
公开(公告)号：US09673280B2
公开(公告)日：2017-06-06
申请号：US11714416
申请日：2007-03-06
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L29/10 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L21/02
CPC分类号： H01L29/1054 , H01L21/02142 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

3. 发明授权

US08319962B2 Mask making decision for manufacturing (DFM) on mask quality control 有权
公开(公告)号：US08319962B2
公开(公告)日：2012-11-27
申请号：US13398165
申请日：2012-02-16
申请人： Chih-Chiang Tu , Chien-Chao Huang
发明人： Chih-Chiang Tu , Chien-Chao Huang
IPC分类号： G01N21/00 , G06K9/00
CPC分类号： G03F1/84
摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.

4. 发明授权

US08288842B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US08288842B2
公开(公告)日：2012-10-16
申请号：US11655008
申请日：2007-01-18
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L23/544 , H01L21/301
CPC分类号： H01L21/78 , B28D5/00
摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.
摘要翻译：一种方法提供用具有金刚石结构的具有基底材料的晶片切割。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

5. 发明授权

US07923759B2 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US07923759B2
公开(公告)日：2011-04-12
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

6. 发明授权

US07582947B2 High performance device design 有权
标题翻译：高性能设备设计
公开(公告)号：US07582947B2
公开(公告)日：2009-09-01
申请号：US11243959
申请日：2005-10-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823412 , H01L21/823481 , H01L29/1037
摘要： A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.
摘要翻译：提供具有凹入的有源区的半导体结构及其形成方法。半导体结构包括在其间具有有源区的第一和第二隔离结构。第一和第二隔离结构具有基本上小于90度的倾斜角的侧壁。活动区域是凹进的。通过使有源区域凹陷，通道宽度增加并且器件驱动电流得到改善。

7. 发明申请

US20080114483A1 Method for Preparing Mask and Wafer Data Files 有权
标题翻译：掩模和晶片数据文件的准备方法
公开(公告)号：US20080114483A1
公开(公告)日：2008-05-15
申请号：US11626218
申请日：2007-01-23
申请人： Hsin-Ying Lee , Chien-Chao Huang , Chih-Chiang Tu
发明人： Hsin-Ying Lee , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F19/00
CPC分类号： G03F1/68 , Y10S707/99945 , Y10S707/99948
摘要： A method for converting a data file into a writer file for a mask writer is provided. A plurality of sub-files is created from the data file. The plurality of sub-files is transferred to the mask writer. A plurality of writer files is created from the plurality of sub-files at the mask writer. The transferring the plurality of sub-files to the mask writer, creating a plurality of writer files from the plurality of sub-files at the mask writer, and checking the plurality of transferred sub-files at the mask writer are executed in parallel in a single process.
摘要翻译：提供了一种用于将数据文件转换成用于掩码写入器的写入器文件的方法。从数据文件创建多个子文件。多个子文件被传送到掩码写入器。在掩码写入器处从多个子文件创建多个写入器文件。将多个子文件传送到掩码写入器，在掩码写入器处从多个子文件创建多个写入器文件，并且在掩码写入器处检查多个传送的子文件，并行执行单一过程。

8. 发明申请

US20080102573A1 CMOS device with raised source and drain regions 有权
标题翻译： CMOS器件具有升高的源极和漏极区域
公开(公告)号：US20080102573A1
公开(公告)日：2008-05-01
申请号：US11588920
申请日：2006-10-27
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.
摘要翻译：形成半导体结构的方法包括形成PMOS器件和NMOS器件。形成PMOS器件的步骤包括在半导体衬底上形成第一栅叠层; 在所述第一栅极堆叠的侧壁上形成第一偏移间隔物; 使用第一偏移间隔件作为掩模在半导体衬底中形成应力器; 并且在应激源上外延生长第一升高的源极/漏极延伸（LDD）区域。形成NMOS器件的步骤包括在半导体衬底上形成第二栅极叠层; 在所述第二栅极堆叠的侧壁上形成第二偏移间隔物; 使用第二偏移间隔物作为掩模在半导体衬底上外延生长第二隆起的LDD区; 以及形成与第二凸起LDD区域相邻的深源极/漏极区域。

9. 发明申请

US20070075356A1 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US20070075356A1
公开(公告)日：2007-04-05
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

10. 发明申请

US20060205164A1 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US20060205164A1
公开(公告)日：2006-09-14
申请号：US11076707
申请日：2005-03-10
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L21/8234
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. Transistors are then formed in close proximity to the trenches and may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：用于隔离沟槽的方法和系统包括在半导体衬底中形成隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境退火以回流沟槽的边缘，从而使边缘变成圆形和悬垂的沟槽。填充材料可以是电介质。晶体管然后形成在沟槽附近，并且可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源/漏区。

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