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1. 发明申请

US20080102573A1 CMOS device with raised source and drain regions 有权
标题翻译： CMOS器件具有升高的源极和漏极区域
公开(公告)号：US20080102573A1
公开(公告)日：2008-05-01
申请号：US11588920
申请日：2006-10-27
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.
摘要翻译：形成半导体结构的方法包括形成PMOS器件和NMOS器件。形成PMOS器件的步骤包括在半导体衬底上形成第一栅叠层; 在所述第一栅极堆叠的侧壁上形成第一偏移间隔物; 使用第一偏移间隔件作为掩模在半导体衬底中形成应力器; 并且在应激源上外延生长第一升高的源极/漏极延伸（LDD）区域。形成NMOS器件的步骤包括在半导体衬底上形成第二栅极叠层; 在所述第二栅极堆叠的侧壁上形成第二偏移间隔物; 使用第二偏移间隔物作为掩模在半导体衬底上外延生长第二隆起的LDD区; 以及形成与第二凸起LDD区域相邻的深源极/漏极区域。

2. 发明授权

US08008157B2 CMOS device with raised source and drain regions 有权
标题翻译： CMOS器件具有升高的源极和漏极区域
公开(公告)号：US08008157B2
公开(公告)日：2011-08-30
申请号：US11588920
申请日：2006-10-27
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.
摘要翻译：形成半导体结构的方法包括形成PMOS器件和NMOS器件。形成PMOS器件的步骤包括在半导体衬底上形成第一栅叠层; 在所述第一栅极堆叠的侧壁上形成第一偏移间隔物; 使用第一偏移间隔件作为掩模在半导体衬底中形成应力器; 并且在应激源上外延生长第一升高的源极/漏极延伸（LDD）区域。形成NMOS器件的步骤包括在半导体衬底上形成第二栅极叠层; 在所述第二栅极堆叠的侧壁上形成第二偏移间隔物; 使用第二偏移间隔物作为掩模在半导体衬底上外延生长第二隆起的LDD区; 以及形成与第二凸起LDD区域相邻的深源极/漏极区域。

3. 发明授权

US09905474B2 CMOS device with raised source and drain regions 有权
公开(公告)号：US09905474B2
公开(公告)日：2018-02-27
申请号：US13210993
申请日：2011-08-16
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

4. 发明申请

US20110298049A1 CMOS Device with Raised Source and Drain Regions 审中-公开
标题翻译： CMOS器件具有引出源和漏极区域
公开(公告)号：US20110298049A1
公开(公告)日：2011-12-08
申请号：US13210993
申请日：2011-08-16
申请人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Chun-Sheng Liang , Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.
摘要翻译：半导体结构包括：包括PMOS区域和NMOS区域的半导体衬底; PMOS区域中的PMOS器件; 和NMOS区域中的NMOS器件。 PMOS器件包括在半导体衬底上的第一栅叠层; 在所述第一栅极堆叠的侧壁上的第一偏移间隔物; 所述半导体衬底中的应力源并且与所述第一偏移间隔物相邻; 以及在所述应力器上并与所述第一偏移间隔物邻接的第一升高的源极/漏极延伸区域，其中所述第一升高的源极/漏极延伸区域具有比所述应力源更高的p型掺杂剂浓度。 NMOS区域中的NMOS器件包括在半导体衬底上的第二栅极堆叠; 在所述第二栅极堆叠的侧壁上的第二偏移间隔物; 在所述半导体衬底上的第二凸起的源极/漏极延伸区域，并邻接所述第二偏移间隔物; 以及与第二升高源极/漏极延伸区域相邻的深源极/漏极区域，其中深的源极/漏极区域没有形成在半导体衬底中的应力源。

5. 发明申请

US20080029831A1 CMOS devices with graded silicide regions 有权
标题翻译：具有分级硅化物区域的CMOS器件
公开(公告)号：US20080029831A1
公开(公告)日：2008-02-07
申请号：US11496857
申请日：2006-08-01
申请人： Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD region, and a graded silicide region on the deep source/drain region and the LDD region. The graded silicide region includes a first portion having a first thickness and a second portion adjoining the first portion and having a second thickness substantially less than the first thickness. The second portion is closer to a channel region than the first portion.
摘要翻译：半导体器件包括半导体衬底，覆盖半导体衬底的栅极堆叠，栅叠层的侧壁上的间隔物，邻近栅叠层的轻掺杂源/漏（LDD）区，与LDD相邻的深源/漏区区域，以及深源极/漏极区域和LDD区域上的渐变硅化物区域。分级硅化物区域包括具有第一厚度的第一部分和与第一部分相邻并具有基本上小于第一厚度的第二厚度的第二部分。第二部分比第一部分更靠近通道区域。

6. 发明授权

US07545006B2 CMOS devices with graded silicide regions 有权
标题翻译：具有分级硅化物区域的CMOS器件
公开(公告)号：US07545006B2
公开(公告)日：2009-06-09
申请号：US11496857
申请日：2006-08-01
申请人： Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
发明人： Hung-Ming Chen , Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD region, and a graded silicide region on the deep source/drain region and the LDD region. The graded silicide region includes a first portion having a first thickness and a second portion adjoining the first portion and having a second thickness substantially less than the first thickness. The second portion is closer to a channel region than the first portion.
摘要翻译：半导体器件包括半导体衬底，覆盖半导体衬底的栅极堆叠，栅叠层的侧壁上的间隔物，邻近栅叠层的轻掺杂源/漏（LDD）区，与LDD相邻的深源/漏区区域，以及深源极/漏极区域和LDD区域上的渐变硅化物区域。分级硅化物区域包括具有第一厚度的第一部分和与第一部分相邻并具有基本上小于第一厚度的第二厚度的第二部分。第二部分比第一部分更靠近通道区域。

7. 发明授权

US08288842B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US08288842B2
公开(公告)日：2012-10-16
申请号：US11655008
申请日：2007-01-18
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L23/544 , H01L21/301
CPC分类号： H01L21/78 , B28D5/00
摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.
摘要翻译：一种方法提供用具有金刚石结构的具有基底材料的晶片切割。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

8. 发明授权

US07923759B2 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US07923759B2
公开(公告)日：2011-04-12
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

9. 发明授权

US07582947B2 High performance device design 有权
标题翻译：高性能设备设计
公开(公告)号：US07582947B2
公开(公告)日：2009-09-01
申请号：US11243959
申请日：2005-10-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823412 , H01L21/823481 , H01L29/1037
摘要： A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.
摘要翻译：提供具有凹入的有源区的半导体结构及其形成方法。半导体结构包括在其间具有有源区的第一和第二隔离结构。第一和第二隔离结构具有基本上小于90度的倾斜角的侧壁。活动区域是凹进的。通过使有源区域凹陷，通道宽度增加并且器件驱动电流得到改善。

10. 发明申请

US20070075356A1 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US20070075356A1
公开(公告)日：2007-04-05
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

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