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1. 发明授权

US07073112B2 Compilable address magnitude comparator for memory array self-testing 失效
标题翻译：可编程地址幅度比较器用于存储器阵列自检
公开(公告)号：US07073112B2
公开(公告)日：2006-07-04
申请号：US10681856
申请日：2003-10-08
申请人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
发明人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/3193 , G11C29/26 , G11C2029/1802
摘要： An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.
摘要翻译：一种改进内置自检（BIST）灵活性的设备。可编译的地址幅度比较器便于对不同大小的存储器阵列进行BIST测试，而无需定制BIST控制器。可编译地址幅度比较器在ASIC的可编译存储器阵列中编译，以允许单个BIST控制器测试多个大小的存储器阵列，而不需要BIST控制器可编译。当BIST尝试测试存储器中不存在的地址时，可编译幅度地址比较器会覆盖BIST的自检信号。 BIST被阻止写入不存在的地址，并且不会从这些地址接收到错误信号。 BIST控制器能够测试存储器阵列，而不考虑其特定大小。单个BIST控制器可用于在ASIC中测试不同大小的多个存储器阵列，从而降低器件的复杂性。

2. 发明授权

US06658610B1 Compilable address magnitude comparator for memory array self-testing 有权
标题翻译：可编程地址幅度比较器用于存储器阵列自检
公开(公告)号：US06658610B1
公开(公告)日：2003-12-02
申请号：US09669117
申请日：2000-09-25
申请人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
发明人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
IPC分类号： G11C2900
CPC分类号： G01R31/3187 , G01R31/3193 , G11C29/26 , G11C2029/1802
摘要： The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory. As such, the BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. Thus, the BIST controller is able to test memory arrays without regard for their particular size. Furthermore, a single BIST controller can then be used to test multiple memory arrays of different sizes in the ASIC, again reducing device complexity.
摘要翻译：本发明提供了一种改进内置自测（BIST）灵活性的方法和装置，而不需要可编译BIST电路的复杂性。此外，本发明提供了使用单个BIST来测试不同大小的多个存储器阵列的能力。本发明的优选实施例提供可编译的地址幅度比较器，以便于不需要定制BIST控制器的不同大小的存储器阵列的BIST测试。优选实施例可编译地址幅度比较器被编译在ASIC的可编译存储器阵列内，以允许单个BIST控制器测试存储器阵列的多个大小，而不需要BIST控制器本身可编译。在优选实施例中，当BIST尝试测试存储器中不存在的地址时，可编译幅度地址比较器覆盖来自BIST的自检信号。因此，BIST被阻止写入不存在的地址，并且不从这些地址接收到错误信号。因此，BIST控制器能够测试存储器阵列，而不考虑其特定大小。此外，可以使用单个BIST控制器来测试ASIC中不同大小的多个存储器阵列，从而降低器件的复杂性。

3. 发明授权

US07586772B2 Method and apparatus for aborting content addressable memory search operations 有权
标题翻译：用于中止内容可寻址存储器搜索操作的方法和装置
公开(公告)号：US07586772B2
公开(公告)日：2009-09-08
申请号：US11462457
申请日：2006-08-04
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael ThaiThanh Phan
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael ThaiThanh Phan
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Content Addressable Memory (CAM) search operations are aborted in response to a search abort signal, thus preserving previous CAM search results. In one embodiment, a CAM search operation is aborted by activating a local CAM match line in response to a search field provided to a CAM and preventing activation of a global CAM match line associated with the local CAM match line in response to a search abort signal. By preventing activation of global CAM match lines, monotonic storage devices included in a holding register that captures CAM search results are prevented from overwriting previously stored CAM search results.
摘要翻译：响应于搜索中止信号，内容可寻址存储器（CAM）搜索操作被中止，从而保留先前的CAM搜索结果。在一个实施例中，通过响应于提供给CAM的搜索字段来激活本地CAM匹配行来中止CAM搜索操作，并且响应于搜索中止信号阻止与本地CAM匹配行相关联的全局CAM匹配行的激活。通过防止全局CAM匹配线的激活，防止包含在捕获CAM搜索结果的保持寄存器中的单调存储设备覆盖先前存储的CAM搜索结果。

4. 发明授权

US06556466B2 Method and structure for a CAMRAM cache memory 失效
公开(公告)号：US06556466B2
公开(公告)日：2003-04-29
申请号：US09842953
申请日：2001-04-26
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thai Thanh Phan
IPC分类号： G11C1500
CPC分类号： G06F12/0893 , G11C15/00
摘要： An improved structure and method of operation are provided wherein a single RAM (random access memory) can be serviced by two CAMs (content addressable memory). This is accomplished by providing first actuating circuitry operably associated with and operatively connecting a first CAM to a selected portion of the RAM and second actuating circuit associated with and operably connecting a second CAM to a second portion of the RAM. The first actuating circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read and circuitry to initiate a CAMRAM index read and index write operably responsive to given control logic. The second circuitry includes circuitry to actuate a selected wordline responsive to a CAM search read and RAM search read responsive to given control logic.

5. 发明授权

US09196330B2 Mimicking multi-voltage domain wordline decoding logic for a memory array 有权
标题翻译：模拟存储器阵列的多电压域字线解码逻辑
公开(公告)号：US09196330B2
公开(公告)日：2015-11-24
申请号：US13424833
申请日：2012-03-20
申请人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen E. Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： G11C8/00 , G11C8/08 , G11C7/12 , G11C8/10 , G11C7/22
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括产生存储器阵列的字线的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线的多电压域模拟逻辑。在一个实施例中，一旦确定了字线，就使用伪字线来触发字线的结束边缘（例如，下降沿）。另外或替代地，伪字线用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

6. 发明授权

US08456929B2 Circuits, systems, and methods for dynamic voltage level shifting 有权
标题翻译：用于动态电压电平转换的电路，系统和方法
公开(公告)号：US08456929B2
公开(公告)日：2013-06-04
申请号：US12755446
申请日：2010-04-07
申请人： Stephen Edward Liles , Chiaming Chai , Lakshmikant Mamileti
发明人： Stephen Edward Liles , Chiaming Chai , Lakshmikant Mamileti
IPC分类号： G11C7/00
CPC分类号： H03K3/356182 , H03K3/356113
摘要： Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.
摘要翻译：公开了动态电压电平移位电路，系统和方法。电平移位电路包括用于接受要移位的第一离散电压电平的输入端，耦合到输入端和第二离散电压电平的电平移位部分，具有使能输入并耦合到电平转换部分的使能部分和输出。电平移位电路被配置为将在第一离散电压电平处的数据输入转换成第二离散电压电平。使能部分被配置为基于使能输入，选择性地将输出的第二离散电压电平或电平移位部分的至少一部分从输出分离。

7. 发明授权

US07761774B2 High speed CAM lookup using stored encoded key 有权
标题翻译：使用存储的编码密钥进行高速CAM查找
公开(公告)号：US07761774B2
公开(公告)日：2010-07-20
申请号：US11262063
申请日：2005-10-28
申请人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
发明人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

8. 发明申请

US20090040801A1 Content Addressable Memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US20090040801A1
公开(公告)日：2009-02-12
申请号：US11836405
申请日：2007-08-09
申请人： Chiaming Chai , David Paul Hoff , Jason Philip Martzloff , Michael ThaiThanh Phan , Manju Rathna Varma
发明人： Chiaming Chai , David Paul Hoff , Jason Philip Martzloff , Michael ThaiThanh Phan , Manju Rathna Varma
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C11/412 , G11C15/04 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/1052
摘要： A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.
摘要翻译：公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元，其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。

9. 发明申请

US20070097722A1 Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground 有权
标题翻译：通过控制虚拟地面对CAMRAM组进行细分的电路和方法
公开(公告)号：US20070097722A1
公开(公告)日：2007-05-03
申请号：US11262062
申请日：2005-10-28
申请人： Michael Phan , Chiaming Chai , Jeffrey Bridges , Jeffrey Fischer
发明人： Michael Phan , Chiaming Chai , Jeffrey Bridges , Jeffrey Fischer
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C8/12 , G11C15/04
摘要： A CAM bank is functionally divided into two or more sub-banks, without replication CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decode from address bits, are distributed to the switching circuits to defined the CAM sub-banks.
摘要翻译：通过禁用组中的所有匹配线放电电路，并且选择性地使能包括子组的放电电路，CAM组在功能上被划分为两个或更多个子组，而不需要复制CAM驱动器电路。至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。可以从地址位解码的控制信号被分配到切换电路以定义CAM子库。

10. 发明授权

US08638153B2 Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width 有权
标题翻译：具有内置电平转换器和可编程上升沿和脉冲宽度的脉冲时钟生成逻辑
公开(公告)号：US08638153B2
公开(公告)日：2014-01-28
申请号：US13433891
申请日：2012-03-29
申请人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
发明人： Shaoping Ge , Chiaming Chai , Stephen Edward Liles , Lam V. Nguyen , Jeffrey Herbert Fischer
IPC分类号： H03K3/00
CPC分类号： G06F1/04 , G11C7/222 , G11C11/417 , G11C11/418 , G11C11/419
摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
摘要翻译：用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法被配置用于不同存储器访问操作的不同需求。脉冲时钟产生电路包括提供脉冲时钟的可编程上升沿延迟的选择性延迟逻辑，提供脉冲时钟可编程脉冲宽度的选择性脉宽扩展逻辑，以及内置电平转换器，脉冲时钟电平。读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

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