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1. 发明授权

US07761774B2 High speed CAM lookup using stored encoded key 有权
标题翻译：使用存储的编码密钥进行高速CAM查找
公开(公告)号：US07761774B2
公开(公告)日：2010-07-20
申请号：US11262063
申请日：2005-10-28
申请人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
发明人： Jeffrey Herbert Fischer , Michael ThaiThanh Phan , Chiaming Chai , James Norris Dieffenderfer
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

2. 发明授权

US10114750B2 Preventing the displacement of high temporal locality of reference data fill buffers 有权
公开(公告)号：US10114750B2
公开(公告)日：2018-10-30
申请号：US13451010
申请日：2012-04-19
申请人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
发明人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
IPC分类号： G06F3/06 , G06F12/0855 , G06F12/0882
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

3. 发明授权

US09460018B2 Method and apparatus for tracking extra data permissions in an instruction cache 有权
标题翻译：用于跟踪指令高速缓存中的额外数据许可的方法和装置
公开(公告)号：US09460018B2
公开(公告)日：2016-10-04
申请号：US13535398
申请日：2012-06-28
申请人： Leslie Mark DeBruyne , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel
发明人： Leslie Mark DeBruyne , James Norris Dieffenderfer , Michael Scott McIlvaine , Brian Michael Stempel
IPC分类号： G06F12/0888 , G06F12/08 , G06F12/14
CPC分类号： G06F12/0875 , G06F12/0886 , G06F12/1416 , G06F12/145
摘要： Systems and methods are disclosed for maintaining an instruction cache including extended cache lines and page attributes for main cache line portions of the extended cache lines and, at least for one or more predefined potential page-crossing instruction locations, additional page attributes for extra data portions of the corresponding extended cache lines. In addition, systems and methods are disclosed for processing page-crossing instructions fetched from an instruction cache having extended cache lines.
摘要翻译：公开了用于维护包括用于扩展高速缓存线的主高速缓存行部分的扩展高速缓存行和页面属性的指令高速缓存的系统和方法，并且至少对于一个或多个预定义的潜在交叉指令位置，用于附加数据部分的附加页面属性的相应扩展缓存行。此外，公开了用于处理从具有扩展高速缓存线的指令高速缓存取出的交叉指令的系统和方法。

4. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

5. 发明授权

US08239657B2 Address translation method and apparatus 有权
标题翻译：地址转换方法和装置
公开(公告)号：US08239657B2
公开(公告)日：2012-08-07
申请号：US11672066
申请日：2007-02-07
申请人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/04
CPC分类号： G06F12/04 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
摘要翻译：通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。

6. 发明申请

US20110320787A1 Indirect Branch Hint 审中-公开
标题翻译：间接分支提示
公开(公告)号：US20110320787A1
公开(公告)日：2011-12-29
申请号：US12824599
申请日：2010-06-28
申请人： James Norris Dieffenderfer , Michael William Morrow
发明人： James Norris Dieffenderfer , Michael William Morrow
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/30003 , G06F9/30101 , G06F9/322 , G06F9/3804 , G06F9/3842
摘要： A processor implements an apparatus and a method for predicting an indirect branch address. A target address generated by an instruction is automatically identified. A predicted next program address is prepared based on the target address before an indirect branch instruction utilizing the target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a predicted indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the predicted indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction.
摘要翻译：处理器实现用于预测间接分支地址的装置和方法。自动识别由指令生成的目标地址。在推测性地执行利用目标地址的间接分支指令之前，基于目标地址准备预测的下一个程序地址。该装置适当地采用寄存器来保存由程序指定的指令存储器地址作为间接分支指令的预测间接地址。该装置还采用下一个程序地址选择器，其从寄存器中选择预测的间接地址作为用于推测性地执行间接分支指令的下一个程序地址。

7. 发明授权

US08078803B2 Apparatus and methods to reduce castouts in a multi-level cache hierarchy 有权
标题翻译：减少多级缓存层次结构中的丢弃的装置和方法
公开(公告)号：US08078803B2
公开(公告)日：2011-12-13
申请号：US11669245
申请日：2007-01-31
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译：技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

8. 发明授权

US07424563B2 Two-level interrupt service routine 有权
标题翻译：两级中断服务程序
公开(公告)号：US07424563B2
公开(公告)日：2008-09-09
申请号：US11361402
申请日：2006-02-24
申请人： Michael Egnoah Birenbach , Gregory Lee Brookshire , James Norris Dieffenderfer , Stephen G. Geist , Richard Alan Moore , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Michael Egnoah Birenbach , Gregory Lee Brookshire , James Norris Dieffenderfer , Stephen G. Geist , Richard Alan Moore , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F13/26
CPC分类号： G06F9/4812
摘要： A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.
摘要翻译：处理器提供两级中断服务。在一个实施例中，处理器包括存储设备和中断处理程序。存储装置被配置为存储对应于中断请求的中断标识符。中断处理程序被配置为识别中断请求，响应于识别中断请求并且随后发起与存储的中断标识符相对应的中断服务程序，启动公共中断服务程序。

9. 发明授权

US07406613B2 Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions 有权
标题翻译：翻译后备缓冲器（TLB）抑制用于页内程序计数器相对或绝对地址分支指令
公开(公告)号：US07406613B2
公开(公告)日：2008-07-29
申请号：US11003772
申请日：2004-12-02
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
IPC分类号： G06F1/26
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对的分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA在同一个页面中，如BTSP位所指示的那样，则抑制对BTA的许可属性的TLB访问被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

10. 发明授权

US07353319B2 Method and apparatus for segregating shared and non-shared data in cache memory banks 有权
标题翻译：用于在高速缓存存储体中隔离共享和非共享数据的方法和装置
公开(公告)号：US07353319B2
公开(公告)日：2008-04-01
申请号：US11144207
申请日：2005-06-02
申请人： Thomas Philip Speier , James Norris Dieffenderfer
发明人： Thomas Philip Speier , James Norris Dieffenderfer
IPC分类号： G06F12/06
CPC分类号： G06F12/0848 , G06F12/0831 , G06F12/0837 , Y02D10/13
摘要： In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated for holding non-shared data. A non-shared data bank may be designated exclusively for holding non-shared data, so that shared data accesses do not interfere with non-shared accesses to that bank. Also, a shared data bank may be designated exclusively for holding shared data, and one or more banks may be designated for holding both shared and non-shared data. An access control circuit directs shared and non-shared accesses to respective banks based on receiving a shared indication signal in association with the accesses. Further, in one or more embodiments, the access control circuit reconfigures one or more bank designations responsive to a bank configuration signal.
摘要翻译：在多处理器系统中，控制对给定处理器的存储高速缓存的访问，使得共享数据访问被定向到指定用于保存共享数据的一个或多个库和/或非共享数据访问被定向到指定用于保存非共享数据的一个或多个库共享数据。非共享数据库可以专门用于保存非共享数据，使得共享数据访问不会干扰对该银行的非共享访问。此外，共享数据库可以被专门用于保存共享数据，并且可以指定一个或多个存储体来保存共享和非共享数据。访问控制电路基于接收与访问相关联的共享指示信号，将共享和非共享访问指向各个存储体。此外，在一个或多个实施例中，访问控制电路响应于存储体配置信号重新配置一个或多个存储体指定。

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