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1. 发明申请

US20140104916A1 SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS 审中-公开
标题翻译：具有存储单元阵列的半导体器件分为多个存储器
公开(公告)号：US20140104916A1
公开(公告)日：2014-04-17
申请号：US14105280
申请日：2013-12-13
申请人： Hiromasa NODA , Yasuji KOSHIKAWA
发明人： Hiromasa NODA , Yasuji KOSHIKAWA
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C8/10 , G11C11/4097
摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
摘要翻译：半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。

2. 发明授权

US08411522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08411522B2
公开(公告)日：2013-04-02
申请号：US13311344
申请日：2011-12-05
申请人： Yasuhiro Matsumoto , Yasuji Koshikawa
发明人： Yasuhiro Matsumoto , Yasuji Koshikawa
IPC分类号： G11C7/02
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.
摘要翻译：半导体器件包括存储单元，耦合到存储单元的位线，彼此相邻布置的第一和第二阱，第一和第二阱彼此不同，导电类型彼此不同，并且在其间界定第一和第二晶体管分别形成在第一和第二阱中，并且沟道类型彼此不同，第一和第二晶体管的栅电极共同连接到位线，并且第三晶体管形成在第一阱中，使得第三阱晶体管夹在边界和第一晶体管之间，并且第三晶体管的栅极被提供有位线预充电信号。

3. 发明申请

US20120075904A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120075904A1
公开(公告)日：2012-03-29
申请号：US13311344
申请日：2011-12-05
申请人： Yasuhiro MATSUMOTO , Yasuji KOSHIKAWA
发明人： Yasuhiro MATSUMOTO , Yasuji KOSHIKAWA
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.
摘要翻译：半导体器件包括存储单元，耦合到存储单元的位线，彼此相邻布置的第一和第二阱，第一和第二阱彼此不同，导电类型彼此不同，并且在其间界定第一和第二晶体管分别形成在第一和第二阱中，并且沟道类型彼此不同，第一和第二晶体管的栅电极共同连接到位线，并且第三晶体管形成在第一阱中，使得第三阱晶体管夹在边界和第一晶体管之间，并且第三晶体管的栅极被提供有位线预充电信号。

4. 发明授权

US07471586B2 Semiconductor memory device which controls refresh of a memory array in normal operation 有权
标题翻译：在正常操作中控制存储器阵列的刷新的半导体存储器件
公开(公告)号：US07471586B2
公开(公告)日：2008-12-30
申请号：US11736421
申请日：2007-04-17
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40622 , G11C2211/4061
摘要： A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.
摘要翻译：半导体存储器件包括刷新计数器，用于当在正常操作中以预定间隔接收到刷新请求时，顺序产生指示与要刷新的一个或多个字线对应的一个或多个行地址的计数值，其中刷新计数器分配给包括在行地址中的n位的n + 1级计数器和不包括在行地址中的伪位，并且从最低有效位到虚拟位的计数器部分形成N进制计数器，以便控制是否在接收刷新请求时响应于虚拟位的值来执行刷新。

5. 发明申请

US20080130394A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080130394A1
公开(公告)日：2008-06-05
申请号：US11987767
申请日：2007-12-04
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.
摘要翻译：半导体存储器件包括：第一刷新周期改变电路，其根据自刷新模式改变刷新周期，而不影响根据自刷新模式的刷新周期;以及第二刷新周期改变电路，其改变刷新根据自刷新模式循环，而不会根据自动刷新模式对刷新周期产生影响。以这种方式，根据本发明，可以独立地控制根据自刷新模式的刷新周期和根据自刷新模式的刷新周期。因此，可以执行考虑每个模式的特性的刷新操作。

6. 发明授权

US07215589B2 Semiconductor memory device that requires refresh operations 有权
标题翻译：需要刷新操作的半导体存储器件
公开(公告)号：US07215589B2
公开(公告)日：2007-05-08
申请号：US11347293
申请日：2006-02-06
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/40622 , G11C11/406 , G11C29/783
摘要： A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the relevant address within one refresh cycle in response to a fact that the ROM circuit detects the relevant address. The multiple refresh control circuit excludes a pattern having a risk that a power supply potential or a ground potential varies greatly such as a pattern that the multiple refresh occurs continuously. With this arrangement, a refresh defective cell can be saved while restricting the variation in the power supply potential or the ground potential.
摘要翻译：一种半导体存储器件，包括输出要刷新的字线的地址的刷新计数器，存储与刷新缺陷地址相关的相关地址的ROM电路，以及同时或连续地激活刷新缺陷地址的多重刷新控制电路以及响应于ROM电路检测到相关地址的事实的一个刷新周期内的相关地址。多重刷新控制电路不包括具有电源电位或接地电位变化很大的风险的图案，例如连续多次刷新的图案。利用这种布置，可以在限制电源电位或地电势的变化的同时，节省刷新故障单元。

7. 发明授权

US07085187B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07085187B2
公开(公告)日：2006-08-01
申请号：US10995465
申请日：2004-11-24
申请人： Yasuji Koshikawa , Chiaki Dono
发明人： Yasuji Koshikawa , Chiaki Dono
IPC分类号： G11C5/14
CPC分类号： G11C11/4094 , G11C7/12 , G11C2207/2227
摘要： A semiconductor storage device in which the chip area is prevented from increasing to reduce the leakage current during low power (power down) time caused by shorting across bit and word lines due to crossing failure. There are provided precharge equalizing NMOS transistors the gates of which are supplied with a control signal (BLEQT). These precharge equalizing NMOS transistors are connected across a power supply line (VNLR), supplying a precharge potential to the bit line, and the bit line. At the time of low power operation, a potential (0.7 to 1.4V) lower than the potential VPP (e.g. 3.2V) applied during the precharge operation of the normal operation is supplied to the gate terminals of the transistors to reduce the leakage current caused by shorting across the bit and word lines caused in turn by crossing failure.
摘要翻译：一种半导体存储装置，其中防止芯片面积增加，以便在由于交叉故障导致的位和字线短路引起的低功率（掉电）时间期间减小漏电流。提供均衡NMOS晶体管的预充电，NMOS晶体管的栅极被提供有控制信号（BLEQT）。这些预充电均衡NMOS晶体管跨越提供给位线的预充电电位和位线的电源线（VNLR）连接。在低功率运行时，在正常工作的预充电操作期间施加的电位VPP（例如3.2V）的电位（0.7〜1.4V）被提供给晶体管的栅极端子，以减少导致的漏电流通过短路通过交叉失败导致的位和字线。

8. 发明申请

US20050117411A1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US20050117411A1
公开(公告)日：2005-06-02
申请号：US10995465
申请日：2004-11-24
申请人： Yasuji Koshikawa , Chiaki Dono
发明人： Yasuji Koshikawa , Chiaki Dono
IPC分类号： G11C11/409 , G11C7/12 , G11C11/407 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C2207/2227
摘要： Disclosed is a semiconductor storage device in which the chip area is prevented from increasing to reduce the leakage current during low power (power down) time caused by shorting across bit and word lines due to crossing failure. There are provided precharge equalizing NMOS transistors the gates of which are supplied with a control signal (BLEQT). These precharge equalizing NMOS transistors are connected across a power supply line (VNLR), supplying a precharge potential to the bit line, and the bit line. At the time of low power operation, a potential (0.7 to 1.4V) lower than the potential VPP (e.g. 3.2V) applied during the precharge operation of the normal operation is supplied to the gate terminals of the transistors to reduce the leakage current caused by shorting across the bit and word lines caused in turn by crossing failure.
摘要翻译：公开了一种半导体存储装置，其中防止芯片面积增加，以便在由于交叉故障导致的位和字线短路引起的低功率（掉电）时间期间减少漏电流。提供均衡NMOS晶体管的预充电，NMOS晶体管的栅极被提供有控制信号（BLEQT）。这些预充电均衡NMOS晶体管跨越提供给位线的预充电电位和位线的电源线（VNLR）连接。在低功率运行时，在正常工作的预充电操作期间施加的电位VPP（例如3.2V）的电位（0.7〜1.4V）被提供给晶体管的栅极端子，以减少导致的漏电流通过短路通过交叉失败导致的位和字线。

9. 发明申请

US20050111282A1 Semiconductor memory device with refreshment control 失效
标题翻译：具有刷新控制的半导体存储器件
公开(公告)号：US20050111282A1
公开(公告)日：2005-05-26
申请号：US10997320
申请日：2004-11-24
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C11/406 , G11C11/407 , G11C29/00 , G11C7/00
CPC分类号： G11C29/783 , G11C11/406 , G11C11/40611 , G11C11/40618
摘要： A semiconductor memory device includes a pair of memory sub arrays and a control signal generating circuit. The pair of memory sub arrays shares a sense amplifier, and each of the pair of memory sub arrays has a plurality of memory cells arranged in a matrix. Each of columns of the matrix is connected to a pair of bit lines, and each of rows of the matrix is connected to a word line. The control signal generating circuit sequentially outputs first and second refresh start signals within an operation time to an external refresh command in response to an internal refresh command. A first refreshing operation is carried out to first memory cells connected to a first word line of one of the memory sub arrays in response to the first refresh start signal, and a second refreshing operation is carried out to second memory cells connected to a second word line different from the first word line in the memory sub array in response to the second refresh start signal.
摘要翻译：半导体存储器件包括一对存储器子阵列和控制信号发生电路。一对存储器子阵列共享读出放大器，并且该对存储器子阵列中的每一个具有以矩阵形式布置的多个存储器单元。矩阵的每列都连接到一对位线，并且矩阵的每行都连接到字线。控制信号发生电路响应于内部刷新命令，在操作时间内顺序地将第一和第二刷新开始信号输出到外部刷新命令。响应于第一刷新开始信号，对连接到存储子阵列之一的第一字线的第一存储器单元执行第一刷新操作，并且对连接到第二字的第二存储单元执行第二刷新操作响应于第二刷新开始信号，与存储器子阵列中的第一字线不同的行。

10. 发明申请

US20050088903A1 Semiconductor memory device of hierarchy word type and sub word driver circuit 有权
标题翻译：层级字类型和子字驱动电路半导体存储器件
公开(公告)号：US20050088903A1
公开(公告)日：2005-04-28
申请号：US10972486
申请日：2004-10-26
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C11/407 , G11C8/08 , G11C8/14 , G11C11/401 , G11C8/00
CPC分类号： G11C8/14 , G11C8/08
摘要： In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.
摘要翻译：在使用主字线信号和子字线信号的分层字结构的半导体存储器件中的子字驱动器电路中，串联连接第一NMOS晶体管和第一PMOS晶体管。第二NMOS晶体管与第一PMOS晶体管和第一NMOS晶体管之间的节点连接。第一PMOS晶体管的源极与通过反相子字线信号而获得的副字线反相信号连接，第一NMOS晶体管的源极与第一负电压连接。单个主字线信号连接到第一PMOS晶体管的栅极和第一NMOS晶体管的栅极，并且子字线信号与第二NMOS晶体管的栅极连接。

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