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1. 发明申请

WO2007112201A9 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
公开(公告)号：WO2007112201A9
公开(公告)日：2008-11-06
申请号：PCT/US2007063863
申请日：2007-03-13
申请人： SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
发明人： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

2. 发明申请

WO2007076503A2 METHOD AND DEVICE FOR POWER-SAVING MULTI-PASS SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中节省多通道感测的方法和装置
公开(公告)号：WO2007076503A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062605
申请日：2006-12-26
申请人： SANDISK CORPORATION , TSAO, Shou-Chang , LI, Yan
发明人： TSAO, Shou-Chang , LI, Yan
CPC分类号： G11C16/26
摘要： Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
摘要翻译：同时采用省电技术来感测一组非易失性存储单元。在一个方面，在预充电操作期间，存储器单元与它们的位线的耦合被延迟，以便减小单元电流抵抗预充电工作。在另一方面，通过在多遍感测操作中预先启动感测来使功耗预充电周期最小化。作为过早感测的结果，未检测到的高电流电流仍然能够在随后的通过中被检测。

3. 发明申请

WO2007112201B1 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
标题翻译：非易失性存储器和冗余数据的方法在数据锁存器中缓存有缺陷的位置
公开(公告)号：WO2007112201B1
公开(公告)日：2008-01-03
申请号：PCT/US2007063863
申请日：2007-03-13
申请人： SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
发明人： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
摘要翻译：存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。用户和冗余部分中的数据锁存器允许从或被写入存储器的数据与数据总线交换。缺陷位置锁存冗余方案假定包括有缺陷列的数据锁存器的列电路仍然可用。用于缺陷列的数据锁存器用于缓冲通常可从冗余部分中的数据锁存器访问的相应冗余数据。以这种方式，用户和冗余数据可从用户数据锁存器获得，并且流数据进出数据总线被简化和性能提高。

4. 发明申请

WO2007112201A3 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
公开(公告)号：WO2007112201A3
公开(公告)日：2007-10-04
申请号：PCT/US2007/063863
申请日：2007-03-13
申请人： SANDISK CORPORATION , MOOGAT, Farookh , CERNEA, Raul-Adrian , TSAO, Shou-Chang , TSENG, Tai-Yuan
发明人： MOOGAT, Farookh , CERNEA, Raul-Adrian , TSAO, Shou-Chang , TSENG, Tai-Yuan
IPC分类号： G11C29/00 , G11C16/26
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

5. 发明申请

WO2007076503A3 NON-VOLATILE MEMORY OPERATED ON. THE BASIS OF A TWO-STEP BIT-LINE PRECHARGE OPERATION AND A TWO-PASS SENSING OPERATION 审中-公开
标题翻译：非易失性存储器操作。两步位线预调操作和两次感测操作的基础
公开(公告)号：WO2007076503A3
公开(公告)日：2007-11-15
申请号：PCT/US2006062605
申请日：2006-12-26
申请人： SANDISK CORP , TSAO SHOU-CHANG , LI YAN
发明人： TSAO SHOU-CHANG , LI YAN
IPC分类号： G11C16/26
CPC分类号： G11C16/26
摘要： Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
摘要翻译：同时采用省电技术来感测一组非易失性存储单元。在一个方面，在预充电操作期间，存储器单元与它们的位线的耦合被延迟，以便减小单元电流抵抗预充电工作。在另一方面，通过在多遍感测操作中预先启动感测来使功耗预充电周期最小化。作为过早感测的结果，未检测到的高电流电流仍然能够在随后的通过中被检测。

6. 发明申请

WO2007112201A2 NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开
标题翻译：非易失性存储器和冗余数据缓存在数据锁存器中用于故障位置的方法
公开(公告)号：WO2007112201A2
公开(公告)日：2007-10-04
申请号：PCT/US2007063863
申请日：2007-03-13
申请人： SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
发明人： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
IPC分类号： G11C29/00 , G11C16/26
CPC分类号： G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
摘要翻译：存储器在其用户部分中具有可由冗余部分中的冗余位置替换的缺陷位置。用户和冗余部分中的数据锁存器允许从存储器读出或写入存储器的数据与数据总线交换。有缺陷的位置锁存冗余方案假定列电路包括有缺陷列的数据锁存器仍然可用。用于缺陷列的数据锁存器用于缓冲通常可从冗余部分的数据锁存器访问的相应冗余数据。通过这种方式，用户数据锁存器和冗余数据都可以从用户数据锁存器中获得，并且流入或流出数据总线的数据流简化并提高了性能。

7. 发明专利

TW200821391A 電子連接材料-錫鋅基無鉛銲錫合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN SYSTEM LEAD-FREE SOLDER ALLOYS 审中-公开
简体标题：电子连接材料-锡锌基无铅焊锡合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN SYSTEM LEAD-FREE SOLDER ALLOYS
公开(公告)号：TW200821391A
公开(公告)日：2008-05-16
申请号：TW095140911
申请日：2006-11-06
申请人：鄭壽昌 CHENG, SHOU CHANG
发明人：鄭壽昌 CHENG, SHOU CHANG , 林靖翔 LIN, J X.
IPC分类号： C22C
摘要：本發明提及錫鋅基三元和四元無鉛銲錫合金,成份包含下列組成一、8.0-12.0 wt% Zn(鋅),10.5-20.0wt% Bi(鉍),其餘為Sn(錫)。二、6.0-12.0 wt% Zn(鋅),0.05-6.0 wt% In(銦),其餘為Sn(錫)。三、6.0-12.0 wt% Zn(鋅),0.05-0.45 wt% Al(鋁),5.0-20.0 wt% Bi(鉍),其餘組成為Sn(錫)。四、6.0-12.0 wt% Zn(鋅),0.05-0.45 wt% Al(鋁),0.05-6.0 wt% In(銦),其餘為Sn(錫)。目前的發明是提供一無鉛銲錫合金來取代鉛錫合金,因鉛錫合金中含有鉛金屬,對人體有害且會造成環境的污染。此發明之無鉛銲錫合金其熔點低於200℃,而且接近鉛錫共晶合金之熔點183.5℃。
简体摘要：本发明提及锡锌基三元和四元无铅焊锡合金,成份包含下列组成一、8.0-12.0 wt% Zn(锌),10.5-20.0wt% Bi(铋),其余为Sn(锡)。二、6.0-12.0 wt% Zn(锌),0.05-6.0 wt% In(铟),其余为Sn(锡)。三、6.0-12.0 wt% Zn(锌),0.05-0.45 wt% Al(铝),5.0-20.0 wt% Bi(铋),其余组成为Sn(锡)。四、6.0-12.0 wt% Zn(锌),0.05-0.45 wt% Al(铝),0.05-6.0 wt% In(铟),其余为Sn(锡)。目前的发明是提供一无铅焊锡合金来取代铅锡合金,因铅锡合金中含有铅金属,对人体有害且会造成环境的污染。此发明之无铅焊锡合金其熔点低于200℃,而且接近铅锡共晶合金之熔点183.5℃。

8. 发明专利

TWI301781B 電子連接材料-錫鋅銀基無鉛銲錫合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN-AG SYSTEM LEAD-FREE SOLDER ALLOYS 失效
简体标题：电子连接材料-锡锌银基无铅焊锡合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN-AG SYSTEM LEAD-FREE SOLDER ALLOYS
公开(公告)号：TWI301781B
公开(公告)日：2008-10-11
申请号：TW095137617
申请日：2006-10-13
申请人：鄭壽昌 CHENG, SHOU-CHANG
发明人：鄭壽昌 CHENG, SHOU-CHANG , 林靖翔 LIN, J X.
IPC分类号： B23K
摘要：本發明提及錫鋅銀基四元和五元無鉛銲錫合金,成份包含下列組成一、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),5-9.8 wt% Bi(鉍),其餘為Sn(錫)。二、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),0.5-8wt% In(銦),其餘為Sn(錫)。三、7-10wt% zn(鋅),0-1 wt% Ag(銀),0-0.3 wt% Al(鋁),5-22 wt% Bi(鉍),其餘組成為Sn(錫)。
四、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),0-0.3 wt% Al(鋁),0-8 wt% In(銦),其餘為Sn(錫)。
目前的發明是提供一無鉛銲錫合金來取代鉛錫合金,因鉛錫合金中含有鉛金屬,對人體有害且會造成環境的污染。此發明之無鉛銲錫合金其熔點低於200℃,而且接近鉛錫共晶合金之熔點183.5℃。
简体摘要：本发明提及锡锌银基四元和五元无铅焊锡合金,成份包含下列组成一、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),5-9.8 wt% Bi(铋),其余为Sn(锡)。二、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),0.5-8wt% In(铟),其余为Sn(锡)。三、7-10wt% zn(锌),0-1 wt% Ag(银),0-0.3 wt% Al(铝),5-22 wt% Bi(铋),其余组成为Sn(锡)。四、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),0-0.3 wt% Al(铝),0-8 wt% In(铟),其余为Sn(锡)。目前的发明是提供一无铅焊锡合金来取代铅锡合金,因铅锡合金中含有铅金属,对人体有害且会造成环境的污染。此发明之无铅焊锡合金其熔点低于200℃,而且接近铅锡共晶合金之熔点183.5℃。

9. 发明专利

TW200817126A 電子連接材料-錫鋅銀基無鉛銲錫合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN-AG SYSTEM LEAD-FREE SOLDER ALLOYS 失效
简体标题：电子连接材料-锡锌银基无铅焊锡合金 ELECTRONIC CONNECTING MATERIALS FOR THE SN-ZN-AG SYSTEM LEAD-FREE SOLDER ALLOYS
公开(公告)号：TW200817126A
公开(公告)日：2008-04-16
申请号：TW095137617
申请日：2006-10-13
申请人：鄭壽昌 CHENG, SHOU CHANG
发明人：鄭壽昌 CHENG, SHOU CHANG , 林靖翔 LIN, J X.
IPC分类号： B23K
摘要：本發明提及錫鋅銀基四元和五元無鉛銲錫合金,成份包含下列組成一、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),5-9.8 wt% Bi(鉍),其餘為Sn(錫)。二、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),0.5-8wt% In(銦),其餘為Sn(錫)。三、7-10wt% zn(鋅),0-1 wt% Ag(銀),0-0.3 wt% Al(鋁),5-22 wt% Bi(鉍),其餘組成為Sn(錫)。四、7-10 wt% Zn(鋅),0-1.0 wt% Ag(銀),0-0.3 wt% Al(鋁),0-8 wt% In(銦),其餘為Sn(錫)。目前的發明是提供一無鉛銲錫合金來取代鉛錫合金,因鉛錫合金中含有鉛金屬,對人體有害且會造成環境的污染。此發明之無鉛銲錫合金其熔點低於200℃,而且接近鉛錫共晶合金之熔點183.5℃。
简体摘要：本发明提及锡锌银基四元和五元无铅焊锡合金,成份包含下列组成一、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),5-9.8 wt% Bi(铋),其余为Sn(锡)。二、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),0.5-8wt% In(铟),其余为Sn(锡)。三、7-10wt% zn(锌),0-1 wt% Ag(银),0-0.3 wt% Al(铝),5-22 wt% Bi(铋),其余组成为Sn(锡)。四、7-10 wt% Zn(锌),0-1.0 wt% Ag(银),0-0.3 wt% Al(铝),0-8 wt% In(铟),其余为Sn(锡)。目前的发明是提供一无铅焊锡合金来取代铅锡合金,因铅锡合金中含有铅金属,对人体有害且会造成环境的污染。此发明之无铅焊锡合金其熔点低于200℃,而且接近铅锡共晶合金之熔点183.5℃。

10. 发明授权

US08159876B2 Non-volatile memory and method for power-saving multi-pass sensing 有权
标题翻译：用于省电多通道感测的非易失性存储器和方法
公开(公告)号：US08159876B2
公开(公告)日：2012-04-17
申请号：US13154223
申请日：2011-06-06
申请人： Shou-Chang Tsao , Yan Li
发明人： Shou-Chang Tsao , Yan Li
IPC分类号： G11C16/04
CPC分类号： G11C7/12 , G11C7/06 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件和省电技术具有降低检测期间的功耗的功能，包括在读取和编程/校验操作中。感测验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，在预充电操作期间，存储器单元与它们的位线的耦合被延迟，以便减小单元电流抵抗预充电工作。在另一方面，通过在多遍感测操作中预先启动感测来使功耗预充电周期最小化。作为过早感测的结果未检测到的高电流电池将在随后的通过中被检测到。

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