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1. 发明授权

US08993424B2 Method for forming a semiconductor transistor device with optimized dopant profile 有权
标题翻译：用于形成具有优化的掺杂剂分布的半导体晶体管器件的方法
公开(公告)号：US08993424B2
公开(公告)日：2015-03-31
申请号：US13288201
申请日：2011-11-03
申请人： Chia-Wen Liu , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
发明人： Chia-Wen Liu , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
IPC分类号： H01L21/425 , H01L21/336 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/165 , H01L21/265
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
摘要翻译：提供了一种用于在半导体器件中形成晶体管的晶体管和方法。该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

2. 发明申请

US20130113041A1 SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE 有权
标题翻译：具有优化的DOPANT轮廓的半导体晶体管器件
公开(公告)号：US20130113041A1
公开(公告)日：2013-05-09
申请号：US13288201
申请日：2011-11-03
申请人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
发明人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
摘要翻译：提供了一种用于在半导体器件中形成晶体管的晶体管和方法。该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

3. 发明申请

US20130113047A1 MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL 有权
公开(公告)号：US20130113047A1
公开(公告)日：2013-05-09
申请号：US13288189
申请日：2011-11-03
申请人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
发明人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/76232 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/167 , H01L29/66492 , H01L29/6659 , H01L29/66651 , H01L29/78 , H01L29/7833
摘要： A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

4. 发明授权

US09000526B2 MOSFET structure with T-shaped epitaxial silicon channel 有权
标题翻译：具有T形外延硅通道的MOSFET结构
公开(公告)号：US09000526B2
公开(公告)日：2015-04-07
申请号：US13288189
申请日：2011-11-03
申请人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
发明人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/76232 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/167 , H01L29/66492 , H01L29/6659 , H01L29/66651 , H01L29/78 , H01L29/7833
摘要： A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
摘要翻译：设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。

5. 发明授权

US09153662B2 MOSFET with selective dopant deactivation underneath gate 有权
标题翻译：栅极下选择性掺杂剂失活的MOSFET
公开(公告)号：US09153662B2
公开(公告)日：2015-10-06
申请号：US13434630
申请日：2012-03-29
申请人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/26506 , H01L21/2658 , H01L29/1045 , H01L29/1608 , H01L29/66537 , H01L29/66545 , H01L29/66651 , H01L29/7833
摘要： A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.
摘要翻译：在衬底上制造金属氧化物半导体场效应晶体管（MOSFET）器件的方法包括用第一类掺杂剂掺杂MOSFET器件的沟道区。源极和漏极在衬底中形成具有第二类型的掺杂剂。选择性掺杂剂失活在MOSFET器件的栅极下方的区域中进行。

6. 发明授权

US08497171B1 FinFET method and structure with embedded underlying anti-punch through layer 有权
标题翻译： FinFET方法和结构具有嵌入式底层抗穿透层
公开(公告)号：US08497171B1
公开(公告)日：2013-07-30
申请号：US13541806
申请日：2012-07-05
申请人： Wei-Hao Wu , Kai-Chieh Yang , Wen-Hsing Hsieh , Ken-Ichi Goto , Zhiqiang Wu
发明人： Wei-Hao Wu , Kai-Chieh Yang , Wen-Hsing Hsieh , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821
摘要： Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.
摘要翻译：用于形成具有优异重复性和可靠性的半导体FinFET器件的方法和结构包括提供准确地形成在半导体鳍片之下的APT（抗穿通）层。在形成半导体翅片的材料形成之前，形成n型和p型APT层。在一些实施例中，在精确定位的APT层和半导体鳍片之间添加阻挡层。使用离子注入方法和外延生长方法在半导体衬底表面中形成适当掺杂的APT层。使用外延生长/沉积方法在APT层上形成翅片材料。

7. 发明申请

US20100102872A1 Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation 审中-公开
标题翻译：用于PMOS晶体管的动态衬底偏置以缓解NBTI降解
公开(公告)号：US20100102872A1
公开(公告)日：2010-04-29
申请号：US12260982
申请日：2008-10-29
申请人： Wei-Hao Wu , Anthony Oates
发明人： Wei-Hao Wu , Anthony Oates
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G05F3/205
摘要： This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.
摘要翻译：本发明公开了一种用于抑制PMOS晶体管中的负偏压温度不稳定性的系统和方法，该系统包括具有连接到电源的源极的PMOS晶体管和被配置为输出第一和第二电压电平的电压控制电路，第一并且第二电压电平彼此不同，第一电压电平低于电源电压，第二电压电平等于或高于电源电压，其中当PMOS晶体管导通时，第一电压电平施加到PMOS晶体管的衬底，并且当PMOS晶体管截止时，第二电压电平被施加到PMOS晶体管的衬底。

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