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1. 发明授权

US08993424B2 Method for forming a semiconductor transistor device with optimized dopant profile 有权
标题翻译：用于形成具有优化的掺杂剂分布的半导体晶体管器件的方法
公开(公告)号：US08993424B2
公开(公告)日：2015-03-31
申请号：US13288201
申请日：2011-11-03
申请人： Chia-Wen Liu , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
发明人： Chia-Wen Liu , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
IPC分类号： H01L21/425 , H01L21/336 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/165 , H01L21/265
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
摘要翻译：提供了一种用于在半导体器件中形成晶体管的晶体管和方法。该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

2. 发明申请

US20130113041A1 SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE 有权
标题翻译：具有优化的DOPANT轮廓的半导体晶体管器件
公开(公告)号：US20130113041A1
公开(公告)日：2013-05-09
申请号：US13288201
申请日：2011-11-03
申请人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
发明人： Chia-Wen LIU , Tsung-Hsing Yu , Dhanyakumar Mahaveer Sathaiya , Wei-Hao Wu , Ken-Ichi Goto , Tzer-Min Shen , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/7833 , Y10S438/931
摘要： Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
摘要翻译：提供了一种用于在半导体器件中形成晶体管的晶体管和方法。该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。使用具有非常低的倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。如此形成的晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。掺杂物分布还包括在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域的晶体管沟道。

3. 发明申请

US20130113047A1 MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL 有权
公开(公告)号：US20130113047A1
公开(公告)日：2013-05-09
申请号：US13288189
申请日：2011-11-03
申请人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
发明人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/76232 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/167 , H01L29/66492 , H01L29/6659 , H01L29/66651 , H01L29/78 , H01L29/7833
摘要： A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

4. 发明授权

US09000526B2 MOSFET structure with T-shaped epitaxial silicon channel 有权
标题翻译：具有T形外延硅通道的MOSFET结构
公开(公告)号：US09000526B2
公开(公告)日：2015-04-07
申请号：US13288189
申请日：2011-11-03
申请人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
发明人： Mahaveer Sathaiya Dhanyakumar , Wei-Hao Wu , Tsung-Hsing Yu , Chia-Wen Liu , Tzer-Min Shen , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762 , H01L29/66 , H01L29/10 , H01L21/265
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/76232 , H01L29/1033 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/167 , H01L29/66492 , H01L29/6659 , H01L29/66651 , H01L29/78 , H01L29/7833
摘要： A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
摘要翻译：设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。

5. 发明授权

US08987824B2 Multi-gate semiconductor devices 有权
标题翻译：多栅极半导体器件
公开(公告)号：US08987824B2
公开(公告)日：2015-03-24
申请号：US13301873
申请日：2011-11-22
申请人： Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Chih-Chieh Yeh , Ken-Ichi Goto , Zhiqiang Wu
发明人： Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Chih-Chieh Yeh , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L27/12 , H01L27/092 , H01L29/78 , H01L29/10
CPC分类号： H01L27/0886 , H01L27/0924 , H01L29/105 , H01L29/7831 , H01L29/7833 , H01L29/785 , H01L29/7851
摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.
摘要翻译：形成包括半导体衬底的多栅极半导体器件。多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。第一晶体管具有形成在其中的第一沟道区。第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。第二浓度高于第一浓度。第一晶体管还包括形成在第一沟道区上的第一栅电极层。第一栅极电极层可以是第二掺杂剂类型。第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。第二沟道区域部分可以形成在第一沟道区域部分上。

6. 发明授权

US08623716B2 Multi-gate semiconductor devices and methods of forming the same 有权
标题翻译：多栅半导体器件及其形成方法
公开(公告)号：US08623716B2
公开(公告)日：2014-01-07
申请号：US13288047
申请日：2011-11-03
申请人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
发明人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L21/00 , H01L21/338 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/7855 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.
摘要翻译：一种多栅半导体器件及其制造方法。形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。第一晶体管具有第一掺杂剂类型的掺杂沟道区。该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。第二晶体管具有第二掺杂剂类型的掺杂沟道区。该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

7. 发明申请

US20130113042A1 MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：多栅极半导体器件及其形成方法
公开(公告)号：US20130113042A1
公开(公告)日：2013-05-09
申请号：US13288047
申请日：2011-11-03
申请人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
发明人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/7855 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.
摘要翻译：一种多栅半导体器件及其制造方法。形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。第一晶体管具有第一掺杂剂类型的掺杂沟道区。该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。第二晶体管具有第二掺杂剂类型的掺杂沟道区。该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

8. 发明授权

US08859380B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08859380B2
公开(公告)日：2014-10-14
申请号：US12944104
申请日：2010-11-11
申请人： Zhiqiang Wu , Yi-Ming Sheu , Tsung-Hsing Yu , Kuan-Lun Cheng , Chih-Pin Tsao , Wen-Yuan Chen , Chun-Fu Cheng , Chih-Ching Wang
发明人： Zhiqiang Wu , Yi-Ming Sheu , Tsung-Hsing Yu , Kuan-Lun Cheng , Chih-Pin Tsao , Wen-Yuan Chen , Chun-Fu Cheng , Chih-Ching Wang
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823468 , H01L29/66492 , H01L29/66545 , H01L29/66575
摘要： A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.
摘要翻译：形成集成电路的方法包括：在衬底上形成沿着第一方向纵向布置的多个栅极结构。对基板执行多个角度离子注入。每个角度离子注入相对于第二方向具有相应的注入角度。第二方向基本上平行于衬底的表面并且基本上与第一方向正交。每个注入角度基本上大于0°。

9. 发明申请

US20050270079A1 Input buffer structure with single gate oxide 有权
标题翻译：具有单栅极氧化物的输入缓冲结构
公开(公告)号：US20050270079A1
公开(公告)日：2005-12-08
申请号：US10859726
申请日：2004-06-03
申请人： Kuo-Ji Chen , Tsung-Hsing Yu , Ker-Min Chen
发明人： Kuo-Ji Chen , Tsung-Hsing Yu , Ker-Min Chen
IPC分类号： H03K5/153 , H03K19/00 , H03K19/0185 , H03L5/00
CPC分类号： H03K19/018521 , H03K19/0027
摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.
摘要翻译：提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。

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