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1. 发明申请

US20120098582A1 Flip-Flop Circuit Design 有权
标题翻译：触发器电路设计
公开(公告)号：US20120098582A1
公开(公告)日：2012-04-26
申请号：US12908602
申请日：2010-10-20
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
IPC分类号： H03K3/356 , H03K3/01
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
摘要翻译：触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

2. 发明申请

US20120023388A1 Parity Look-Ahead Scheme for Tag Cache Memory 有权
标题翻译：标签缓存内存的奇偶性前瞻方案
公开(公告)号：US20120023388A1
公开(公告)日：2012-01-26
申请号：US12842676
申请日：2010-07-23
申请人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： G06F11/10
CPC分类号： G06F12/0875 , G06F11/1064 , H03M13/098
摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
摘要翻译：一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

3. 发明授权

US08416002B2 Flip-flop circuit design 有权
标题翻译：触发电路设计
公开(公告)号：US08416002B2
公开(公告)日：2013-04-09
申请号：US12908602
申请日：2010-10-20
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
摘要翻译：触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

4. 发明授权

US08359528B2 Parity look-ahead scheme for tag cache memory 有权
标题翻译：标签高速缓冲存储器的奇偶校验方案
公开(公告)号：US08359528B2
公开(公告)日：2013-01-22
申请号：US12842676
申请日：2010-07-23
申请人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： H03M13/00
CPC分类号： G06F12/0875 , G06F11/1064 , H03M13/098
摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
摘要翻译：一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

5. 发明授权

US08116149B2 Circuit and method for small swing memory signals 有权
标题翻译：小摆动记忆信号的电路和方法
公开(公告)号：US08116149B2
公开(公告)日：2012-02-14
申请号：US12687571
申请日：2010-01-14
申请人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C7/06
CPC分类号： G11C8/12 , G11C11/413
摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.
摘要翻译：描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。多个存储单元形成为多个存储体中的阵列。每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。公开了向存储器单元提供小的摆动全局位线信号的方法。在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

6. 发明授权

US08405441B2 Latch circuitry and methods of operating latch circuitry 有权
标题翻译：锁存电路和操作锁存电路的方法
公开(公告)号：US08405441B2
公开(公告)日：2013-03-26
申请号：US13070868
申请日：2011-03-24
申请人： Chien-Kuo Su , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chien-Kuo Su , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： H03K3/356
CPC分类号： H03K3/012 , H03K3/356121 , H03K3/356173
摘要： A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.
摘要翻译：锁存电路包括与电路电耦合的输出驱动器。电路通过第一路径和第二路径与输出驱动器电耦合。电路被配置为接收数据信号。电路被配置为在数据信号的下降沿通过第一路径转移输出驱动器的信号。电路被配置为在数据信号的上升沿通过第二路径转移输出驱动器的信号。

7. 发明申请

US20100260002A1 Circuit and Method for Small Swing Memory Signals 有权
标题翻译：小型摆动存储器信号的电路和方法
公开(公告)号：US20100260002A1
公开(公告)日：2010-10-14
申请号：US12687571
申请日：2010-01-14
申请人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
发明人： Yi-Tzu Chen , Chia-Wei Su , Ming-Zhang Kuo , Chung-Cheng Chou
IPC分类号： G11C7/02 , G11C8/00
CPC分类号： G11C8/12 , G11C11/413
摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.
摘要翻译：描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。多个存储单元形成为多个存储体中的阵列。每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。公开了向存储器单元提供小的摆动全局位线信号的方法。在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

8. 发明授权

US08575965B2 Internal clock gating apparatus 有权
标题翻译：内部时钟选通装置
公开(公告)号：US08575965B2
公开(公告)日：2013-11-05
申请号：US13118060
申请日：2011-05-27
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
IPC分类号： H03K19/096
CPC分类号： G06F1/3287 , G06F1/3237 , Y02D10/128 , Y02D10/171
摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.
摘要翻译：内部时钟选通装置包括静态逻辑块和多米诺逻辑块。静态逻辑块被配置为接收时钟信号和时钟使能信号。多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

9. 发明申请

US20120299622A1 Internal Clock Gating Apparatus 有权
标题翻译：内部时钟门控器
公开(公告)号：US20120299622A1
公开(公告)日：2012-11-29
申请号：US13118060
申请日：2011-05-27
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
IPC分类号： H03K19/096
CPC分类号： G06F1/3287 , G06F1/3237 , Y02D10/128 , Y02D10/171
摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.
摘要翻译：内部时钟选通装置包括静态逻辑块和多米诺逻辑块。静态逻辑块被配置为接收时钟信号和时钟使能信号。多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

10. 发明授权

US08724420B2 SRAM write assist apparatus 有权
标题翻译： SRAM写入辅助装置
公开(公告)号：US08724420B2
公开(公告)日：2014-05-13
申请号：US13105382
申请日：2011-05-11
申请人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
IPC分类号： G11C11/413
CPC分类号： G11C11/419 , G11C11/41 , G11C29/021 , G11C29/023 , G11C29/028
摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.
摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。分压器单元被配置为将电压电位分压到较低电平。在写入操作中，分压器的输出连接到存储单元。定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

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